DHQ1ECCSECETS1SR1WH 查看數據表（PDF） - Intel
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DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Legacy Bridge—Intel® Quark SoC X1000
Table 133. Summary of I/O Registers (Continued)
Offset
Start
25h
28h
29h
2Dh
A0h
A1h
A4h
A5h
A8h
A9h
ADh
4D0h
4D1h
Offset
End
25h
28h
29h
2Dh
A0h
A1h
A4h
A5h
A8h
A9h
ADh
4D0h
4D1h
Register ID—Description
“Master Initialization Command Word 3 (MICW3)—Offset 25h” on
page 895
“Master Operational Control Word 3 (MOCW3)—Offset 28h” on
page 895
“Master Initialization Command Word 4 (MICW4)—Offset 29h” on
page 896
“Master Operational Control Word 1 (MOCW1)—Offset 2Dh” on
page 897
“Slave Initialization Command Word 1 (SICW1)—Offset A0h” on
page 897
“Slave Initialization Command Word 2 (SICW2)—Offset A1h” on
page 898
“Slave Operational Control Word 2 (SoCW2)—Offset A4h” on
page 898
“Slave Initialization Command Word 3 (SICW3)—Offset A5h” on
page 899
“Slave Operational Control Word 3 (SoCW3)—Offset A8h” on
page 899
“Slave Initialization Command Word 4 (SICW4)—Offset A9h” on
page 900
“Slave Operational Control Word 1 (SoCW1)—Offset ADh” on
page 901
“Master Edge/Level Control (ELCR1)—Offset 4D0h” on page 901
“Slave Edge/Level Control (ELCR2)—Offset 4D1h” on page 901
Default
Value
E7h
19Eh
421h
00h
81Fh
63h
67h
E7h
19Eh
421h
00h
108h
14Ah
21.12.3.1 Master Initialization Command Word 1 (MICW1)—Offset 20h
A write to Initialization Command Word 1 starts the interrupt controller initialization
sequence, during which the following occurs:
• The Interrupt Mask register is cleared.
• IRQ7 input is assigned priority 7.
• The slave mode address is set to 7.
• Special Mask Mode is cleared and Status Read is set to IRR.
Once this write occurs, the controller expects writes to ICW2, ICW3, and ICW4 to
complete the initialization sequence.
Access Method
Type: I/O Register
(Size: 8 bits)
MICW1: 20h
7
4
0
X
X
X
X
X
X
X
X
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
893
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