DHQ1ECCSECETS1SR1WH 查看數據表（PDF） - Intel

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DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Intel® Quark SoC X1000—Legacy Bridge

21.12.3.9

Bit

Default &

Range Access

Description

7: 5

4

3

2

1

0

X

MCS85 (MCS85): These bits are MCS-85 specific, and not needed. Should be

WO

programmed to 000

X

ICW/OCW select (ICWOCWSEL): This bit must be a 1 to select ICW1 and enable the

WO

ICW2, ICW3, and ICW4 sequence.

X

WO

Edge/Level Bank Select (LTIM): Disabled. Replaced by ELCR1 and ELCR2.

X

WO

ADI (ADI): Should be programmed to 0.

X

Single or Cascade (SNGL): Must be programmed to a 0 to indicate two controllers

WO

operating in cascade mode.

X

wICW4 Write Required (IC4): This bit must be programmed to a 1 to indicate that

WO

ICW4 needs to be programmed.

Slave Initialization Command Word 2 (SICW2)—Offset A1h

Slave ICW2 is used to initialize the interrupt controller with the five most significant bits

of the interrupt vector address. The value programmed for bits[7:3] is used by the CPU

to define the base address in the interrupt vector table for the interrupt routines

associated with each IRQ on the controller. Typical ISA ICW2 values are 08h for the

master controller and 70h for the slave controller.

Access Method

Type: I/O Register

(Size: 8 bits)

SICW2: A1h

7

4

0

X

X

X

X

X

X

X

X

Bit

Default &

Range Access

Description

7: 3

2: 0

X

WO

Interrupt Vector Base Address (IVBA): Bits [7:3] define the base address in the

interrupt vector table for the interrupt routines associated with each interrupt request

level input.

Interrupt Request Lever (IRL): When writing ICW2, these bits should all be 0.

During an interrupt acknowledge cycle, these bits are programmed by the interrupt

controller with the interrupt to be serviced. This is combined with bits [7:3] to form the

interrupt vector driven onto the data bus during the second INTA# cycle. The code is a

three bit binary code:

X

Code Master Interrupt Slave Interrupt

000 IRQ0

IRQ8

WO

001 IRQ1

010 IRQ2

IRQ9

IRQ10

011 IRQ3

IRQ11

100 IRQ4

IRQ12

101 IRQ5

IRQ13

110 IRQ6

IRQ14

111 IRQ7

IRQ15

21.12.3.10 Slave Operational Control Word 2 (SoCW2)—Offset A4h

Following a part reset or ICW initialization, the controller enters the fully nested mode

of operation. Non-specific EOI without rotation is the default. Both rotation mode and

specific EOI mode are disabled following initialization.

Access Method

Intel® Quark SoC X1000

DS

898

October 2013

Document Number: 329676-001US

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