DHQ1ECCSECETS1SR1WH 查看數據表（PDF） - Intel

零件编号

产品描述 (功能)

生产厂家

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Intel® Quark SoC X1000—Legacy Bridge

Type: I/O Register

(Size: 8 bits)

MOCW3: 28h

7

4

0

0

0

1

X

X

X

1

0

21.12.3.6

Bit

Default &

Range Access

Description

7

6

5

4: 3

2

1: 0

0b

RO

RESERVED (RESERVED): Must be 0.

0b

Special Mask Mode (SMM): If this bit is set, the Special Mask Mode can be used by an

interrupt service routine to dynamically alter the system priority structure while the

WO

routine is executing, through selective enabling/ disabling of the other channel's mask

bits. Bit 6, the ESMM bit, must be set for this bit to have any meaning.

1b

Enable Special Mask Mode (ESMM): When set, the SMM bit is enabled to set or reset

WO

the Special Mask Mode. When cleared, the SMM bit becomes a don't care.

X

WO

OCW3 Select (O3S): When selecting OCW3, bits 4:3 = 01

X

Poll Mode Command (PMC): When cleared, poll command is not issued. When set,

the next I/O read to the interrupt controller is treated as an interrupt acknowledge

WO

cycle. An encoded byte is driven onto the data bus, representing the highest priority

level requesting service.

Register Read Command (RRC): These bits provide control for reading the ISR and

Interrupt IRR. When bit 1=0, bit 0 will not affect the register read selection. Following

ICW initialization, the default OCW3 port address read will be read IRR. To retain the

10b

WO

current selection (read ISR or read IRR), always write a 0 to bit 1 when programming

this register. The selected register can be read repeatedly without reprogramming

OCW3. To select a new status register, OCW3 must be reprogrammed prior to

attempting the read.

00 No Action 01 No Action

10 Read IRQ Register 11 Read IS Register

Master Initialization Command Word 4 (MICW4)—Offset 29h

Access Method

Type: I/O Register

(Size: 8 bits)

MICW4: 29h

7

4

0

X

X

X

0

0

0

0

1

Bit

Default &

Range Access

Description

7: 5

4

3

X

WO

MBZ (MBZ): These bits must be programmed to zero.

0b

Special Fully Nested Mode (SFNM): Should normally be disabled by writing a 0 to

WO

this bit. If SFNM=1, the special fully nested mode is programmed.

0b

Buffered Mode (BUF): Must be cleared for non-buffered mode. Writing 1 will result in

WO

undefined behavior.

Intel® Quark SoC X1000

DS

896

October 2013

Document Number: 329676-001US

Share Link: