DHQ1ECCSECETS1SR1WH 查看數據表（PDF） - Intel
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DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Legacy Bridge—Intel® Quark SoC X1000
7
4
0
0
0
0
0
0
0
0
0
Bit
Default &
Range Access
Description
7:6
0b
RO
Reserved (RSV2): Reserved.
WDT Timeout Output Enable (WDT_TOUT_EN): This bit indicates whether or not
5
0b
RW
the WDT toggles the external WDT_TOUT signal if the WDT times out.
0 = Enabled (Default)
1 = Disabled
WDT Reset Enable (WDT_RESET_EN): When this bit is enable (set to 1), it allows
4
0b
RW
internal reset to be trigger when WDT timeout in the second stage. It either trigger
COLD or WARM reset depend on WDT_RESET_SEL bit.
0 = Disable internal reset (Default)
1 = Enable internal COLD or WARM reset.
WDT Reset Select (WDT_RESET_SEL): This determines which reset to be triggered
3
0b
RW
when WDT_RESET_EN is set.
0 = Cold Reset (Default)
1 = Warm Reset
WDT Prescaler Select (WDT_PRE_SEL): The WDT provides two options for
prescaling the main Down Counter. The preload values are loaded into the main down
counter right justified. The prescaler adjusts the starting point of the 35-bit down
counter.
2
0b
RW
0 = The 20-bit Preload Value is loaded into bits 34:15 of the main down counter. The
resulting timer clock is the PCI Clock (33 MHz) divided by 2^15. The approximate clock
generated is 1 KHz, (1 ms to 10 min). (Default)
1 = The 20-bit Preload Value is loaded into bits 24:05 of the main down counter. The
resulting timer clock is the PCI Clock (33 MHz) divided by 2^5. The approximate clock
generated is 1 MHz, (1 us to 1sec)
1:0
0b
RO
Reserved (RSVD): Reserved.
21.14.4.10 WDT Lock Register (WDTLR)—Offset 18h
Access Method
Type: I/O Register
(Size: 8 bits)
WDTLR: [WDTBA] + 18h
WDTBA Type: PCI Configuration Register (Size: 32 bits)
WDTBA Reference: [B:0, D:31, F:0] + 84h
Default: 00h
7
4
0
0
0
0
0
0
0
0
0
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
917
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