DHQ1ECCSECETS1SR1WH 查看數據表（PDF） - Intel
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DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Debug Port and JTAG/TAP—Intel® Quark SoC X1000
22.0 Debug Port and JTAG/TAP
The Intel® Quark SoC X1000 provides a TAP (Test Access Port) Controller interface that
aids in the debug and test of the SoC. The TAP Controller interface can be used for
debug by attaching a JTAG-based debugger. The SoC supports the open source Open
On-Chip Debugger (OpenOCD) tools.
22.1
Signal Descriptions
Please see Chapter 2.0, “Physical Interfaces” for additional details.
The signal description table has the following headings:
• Signal Name: The name of the signal/pin
• Direction: The buffer direction can be either input, output, or I/O (bidirectional)
• Type: The buffer type found in Chapter 4.0, “Electrical Characteristics”
• Description: A brief explanation of the signal’s function
Table 137. Debug Port and JTAG/TAP Signals
Signal Name
TCK
TDI
TDO
TMS
TRST_B
PREQ_B
PRDY_B
Direction/
Type
Description
I
CMOS3.3
I
CMOS3.3
O
CMOS3.3
I
CMOS3.3
I
CMOS3.3
I
CMOS3.3
O
CMOS3.3
JTAG Test Clock
Provides the clock input for TAP controller. Maximum frequency is 25
MHz.
JTAG Test Data In
TDI is used to serially shift data and instructions into the TAP.
JTAG Test Data Out
TDO is used to serially shift data out of the TAP.
JTAG Test Mode Select
This signal is used to control the state of the TAP controller.
JTAG Test Reset
Asynchronously resets the TAP logic.
Probe Mode Request
Used to request entry into Probe Mode.
Probe Mode Ready
Indicates Probe Mode has been entered.
Note:
PREQ_B and PRDY_B are not needed for OpenOCD-based debug.
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
919
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