DHQ1ECCSECETS1SR1WH 查看數據表（PDF） - Intel

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DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Intel® Quark SoC X1000—Legacy Bridge

Bit

Default &

Range Access

Description

7:3

0b

RO

Reserved (RSV): Reserved.

WDT Timeout Configuration (WDT_TOUT_CNF): This register is used to choose the

functionality of the timer.

2

0b

RW

0 = Watchdog Timer Mode: When enabled (i.e. WDT_ENABLE goes from 0 to 1) the

timer reloads Preload Value 1 and start decrementing. (Default) Upon reaching the

second stage timeout the WDT_TOUT is driven high once and does not change again

until Power is cycled or a hard reset occurs.

1 = Reserved

Watchdog Timer Enable (WDT_ENABLE): The following bit enables or disables the

WDT.

0 = Disabled (Default)

1 = Enabled

1

0b

RW

Note: This bit cannot be modified if WDT_LOCK has been set.

Note: In WDT mode Preload Value 1 is reloaded every time WDT_ENABLE goes from 0 to

1 or the WDT_RELOAD bit is written using the proper sequence of writes (See Register

Unlocking Sequence). When the WDT second stage timeout occurs, a reset must

happen.

Note: Software must guarantee that a timeout is not about to occur before disabling the

timer. A reload sequence is suggested.

Watchdog Timer Lock (WDT_LOCK): Setting this bit locks the values of this register

until a hard-reset occurs or power is cycled.

0

0b

RW/O

0 = Unlocked (Default)

1 = Locked

Note: Writing a 0 has no effect on this bit. Write is only allowed from 0 to 1 once. It

cannot be changed until either power is cycled or a hard reset occurs

§§

Intel® Quark SoC X1000

DS

918

October 2013

Document Number: 329676-001US

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