CSR8635 查看數據表（PDF） - CSR plc
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CSR8635 Datasheet PDF : 105 Pages
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5 Kalimba DSP
The Kalimba DSP is an open platform DSP enabling signal processing functions to be performed on over‑air data or
codec data to enhance audio applications. Figure 5.1 shows the Kalimba DSP interfaces to other functional blocks
within CSR8635 QFN.
Kalimba DSP Core
MCU Register Interface (including Debug)
Memory
Management
Unit
DSP MMU Port
7, 2013 DSP, MCU and Memory Window Control
mber 2 Programmable Clock = 80MHz
iday, Septe DSP RAMs
- Fr DM2
om.cn DM1
lpoint.c PM
DSP Data Memory 2 Interface (DM2)
DSP Data Memory 1 Interface (DM1)
DSP Program Memory Interface (PM)
Data Memory
Inteface
Address
Generators
Instruction Decode
ALU
Program Flow
DEBUG
Clock Select
PIO
Internal Control Register
MMU Interface
Interrupt Controller
Timer
MCU Window
Flash Window
PIO In/Out
IRQ to Subsystem
IRQ from Subsystem
1µs Timer Clock
hou - exce Figure 5.1: Kalimba DSP Interface to Internal Functions
en.z The key features of the DSP include:
kev ■ 80MIPS performance, 24‑bit fixed point DSP core
bo ■ Single‑cycle MAC; 24 x 24‑bit multiply and 56‑bit accumulate includes 2 rMAC registers and new instructions
ing for improved performance over previous architecture
r q ■ 32‑bit instruction word
fo ■ Separate program memory and dual data memory, enabling an ALU operation and up to 2 memory accesses
red in a single cycle
pa ■ Zero overhead looping, including a very low‑power 32‑instruction cache
Pre ■ Zero overhead circular buffer indexing
■ Single cycle barrel shifter with up to 56‑bit input and 56‑bit output
■ Multiple cycle divide (performed in the background)
■ Bit reversed addressing
■ Orthogonal instruction set
■ Low overhead interrupt
For more information see Kalimba Architecture 3 DSP User Guide.
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© Cambridge Silicon Radio Limited 2013
Confidential Information - This Material is Subject to CSR's Non-disclosure Agreement
Page 29 of 105
CS-303725-DSP5
www.csr.com
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