DSPIC30F2012AT-20E/ML-ES 查看數據表（PDF） - Microchip Technology

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DSPIC30F2012AT-20E/ML-ES

High-Performance, 16-bit Digital Signal Controllers

Microchip Technology 

dsPIC30F2011/2012/3012/3013

11.0 INPUT CAPTURE MODULE

Note:

This data sheet summarizes features of

this group of dsPIC30F devices and is not

intended to be a complete reference

source. For more information on the CPU,

peripherals, register descriptions and

general device functionality, refer to the

“dsPIC30F Family Reference Manual”

(DS70046).

This section describes the input capture module and

associated operational modes. The features provided

by this module are useful in applications requiring

frequency (period) and pulse measurement.

Figure 11-1 depicts a block diagram of the input

capture module. Input capture is useful for such modes

as:

• Frequency/Period/Pulse Measurements

• Additional Sources of External Interrupts

Important operational features of the input capture

module are:

• Simple Capture Event mode

• Timer2 and Timer3 mode selection

• Interrupt on input capture event

These operating modes are determined by setting the

appropriate bits in the IC1CON and IC2CON registers.

The dsPIC30F2011/2012/3012/3013 devices have two

capture channels.

11.1 Simple Capture Event Mode

The simple capture events in the dsPIC30F product

family are:

• Capture every falling edge

• Capture every rising edge

• Capture every 4th rising edge

• Capture every 16th rising edge

• Capture every rising and falling edge

These simple Input Capture modes are configured by

setting the appropriate bits, ICM<2:0> (ICxCON<2:0>).

11.1.1 CAPTURE PRESCALER

There are four input capture prescaler settings

specified by bits ICM<2:0> (ICxCON<2:0>). Whenever

the capture channel is turned off, the prescaler counter

is cleared. In addition, any Reset clears the prescaler

counter.

FIGURE 11-1:

INPUT CAPTURE MODE BLOCK DIAGRAM

From GP Timer Module

T2_CNT T3_CNT

ICx pin

Prescaler

1, 4, 16

Clock

Synchronizer

3

ICM<2:0>

Mode Select

ICBNE, ICOV

Edge

Detection

Logic

ICxCON

ICI<1:0>

Interrupt

Logic

FIFO

R/W

Logic

16 16

ICTMR

10

ICxBUF

Note:

Data Bus

Set Flag

ICxIF

Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture

channel (1 or 2).

© 2008 Microchip Technology Inc.

DS70139F-page 83

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