CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

10.3.52 SDENDA (0x184) — Sound DMA End A

31 30 29

12 11

43

0

S L XXXXXXXXXXXXXXXXXX EEEEEEEE 0000

Program this register with the offset within the page of the final qword. Bit 30 should always be pro-

grammed to ‘0’, unless the channel is being initialized for a single transfer – when it must be programmed

high.

S

stop bit

L

last bit

E

end[11:0]

Write

bit[31] stop bit:

0

do not stop after reaching End

1

stop after reaching End

bit[30] last bit

0

not last transfer

1

last qword transfer

bits[11:4] last DMA location within page selected

bits[3:0] ignored

Read

bits[31:30, 11:4] value written

bits[3:0] always ‘0’

10.3.53 SDCURB (0x188) — Sound DMA Current B

31

29 28

12 11

43

0

X X X PPPPPPPPPPPPPPPPP F F F F F F F F 0 0 0 0

The B pair of registers for the sound DMA channel are used in exactly the same way as the A pair, to

enable DMA to continue from the page addressed by one set of registers while the other set are being

reprogrammed.

P

page[16:0]

F

offset[11:0]

Write

bits[31:29] unused

bits[28:12] page of next DMA fetch

bits[11:4] offset within page of next DMA fetch

bits[3:0] ignored

Read

bits[31:29] undefined

bits[28:4] current DMA fetch location

bits[3:0] always ‘0’

100

MEMORY AND I/O PROGRAMMERS’ MODEL

ADVANCE DATA BOOK v2.0

June 1997

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