CL-PS7500FE
System-on-a-Chip for Internet Appliance
10.3.54 SDENDB (0x18C) — Sound DMA End B
31 30 29
12 11
43
0
S L XXXXXXXXXXXXXXXXXX EEEEEEEE 0000
This register is used in the same way as the SDENDA register.
S
stop bit
L
last bit
E
end[11:0]
Write
bit[31] stop bit
0
do not stop after reaching end
1
stop after reaching end
bit[30] last bit
0
not last transfer
1
last qword transfer
bits[11:4] last DMA location within page selected
bits[3:0] ignored
Read
bits[31:30, 11:4] value written
bits[3:0] always ‘0’
June 1997
ADVANCE DATA BOOK v2.0
MEMORY AND I/O PROGRAMMERS’ MODEL
101