CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

10.3.60 VIDCURA (0x1D0) — Video DMA Current A

31

29 28

43

0

X X X CCCCCCCCCCCCCCCCCCCCCCCCC 0 0 0 0

C

Write

Read

current fetch location A

bits[31:29] unused

bits[28:4] video current A DMA fetch location

bits[3:0] ignored

bits[31:29] undefined

bits[28:4] video current A DMA fetch location

bits[3:0] always ‘0’

10.3.61 VIDEND (0x1D4) — Video DMA End

31

43

0

XX X X X X X X E E E E E E E E E E E E E E E E E E E E E 0 0 0 0

Load the Video End register with the address of the final qword of the video frame buffer within memory

E

end location

Write

bits[31:24] unused

bits[23:4] video end location

bits[3:0] ignored

Read

bits[31:24] undefined

bits[23:4] video end location

bits[3:0] always ‘0’

10.3.62 VIDSTART (0x1D8) — Video DMA Start

31

29 28

43

0

X X X SSSSSSSSSSSSSSSSSSSSSSSSS 0000

Load the Video Start register with the location of the first qword at the start of the video frame buffer. All

the DMA control registers can only be loaded with qword-aligned values.

S

start location

Write

bits[31:29] unused

bits[28:4] video DMA start fetch location

bits[3:0] ignored

Read

bit[31:29] undefined

bits[28:4] video DMA start fetch location

bits[3:0] always ‘0’

104

MEMORY AND I/O PROGRAMMERS’ MODEL

ADVANCE DATA BOOK v2.0

June 1997

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