CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

10.3.55 SDCR (0x190) — Sound DMA Control

76543210

C0E1 0 0 0 0

This register controls the sound DMA channel and its state machine. Only two bits can be written to:

¥ bit 7 clears the state machine into a state where it has overrun and is requesting an interrupt.

¥ bit 6 enables the sound DMA channel.

C

clear

E

enable

Write

bit[7] clear

0

do not clear state machine

1

clear state machine. Self clearing

bit[6] not used

bit[5] enable

0

disabled

1

enabled

bits[4:0] not used

Read

bit[7] always reads ‘0’

bit[6] always reads ‘0’

bit[5] enable

0

disabled

1

enabled

bits[4:0] read as ‘10000’ (binary), indicating a qword transfer

Reset

enable set to ‘0’

10.3.56 SDST (0x194) — Sound DMA Status

76543210

XXXXXO I W

The sound DMA status register shows the status of the state machine that controls sound DMA accesses.

It cannot be written to.

O

overrun

I

interrupt request

W

A or B buffer indication

Write

ignored

Read

bits[7:3] unused

bits[2:0] direct state machine state

Reset

set to ‘110’ (binary)

102

MEMORY AND I/O PROGRAMMERS’ MODEL

ADVANCE DATA BOOK v2.0

June 1997

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