CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

21. CLOCKS, POWER SAVING, AND RESET

21.1 Clock Control

CL-PS7500FE has a clocking scheme designed to allow maximum flexibility for the system designer.

There are three main clock inputs:

q CPUCLK — CPU clock, used to generate the ARM processor’s FCLK

q MEMCLK — Memory subsystem clock, used to generate the memory system clock, and the ARM processor

MCLK

q I_OCLK — I/O system clock, this is fixed at 32 MHz and generates all the fixed-frequency I/O clocks and

refresh rates.

21.1.1 Video and Sound Subsystem Clocks

The video subsystem has two separate external clock inputs and includes a phase-locked loop to enable

the control of an external VCO.

The pixel clock source can be VCLKI (selected by using an external VCO), HCLK, driven directly in from

the HCLK pin, or IOCK32 (also referred to as RCLK), which is the internal I/O subsystem clock and is

generated directly from the main I_OCLK input pin as described below. The sound subsystem can be

clocked either from IOCK32 generated internally from I_OCLK, or by using an externally generated clock

connected to the SCLK pin.

Selection between these various clock sources is described in the video and sound sub-systems section

of this data sheet.

21.1.2 I/O Clock Outputs

Four fixed frequency I/O clocks are output by the CL-PS7500FE, all divided down from the fixed frequency

input I_OCLK, set to 32 MHz in Divide-by-1 mode. These are:

q CLK16 (16 MHz)

q REF8M (8 MHz)

q CLK8 (An inverted version of REF8M)

q CLK2 (2 MHz)

21.1.3 Synchronous/Asynchronous Mode for the ARM Processor

The ARM processor macrocell can be configured for synchronous or asynchronous mode, under the con-

trol of the SnA pin. Synchronous mode can only be used within the CL-PS7500FE if the internal ARM

processor clocks, FCLK and MCLK, are of exactly the same fundamental frequency and timing, and in

fact when SnA is set high, MEMCLK is routed straight through to drive both FCLK and MCLK, with a suit-

able delay to ensure the required phase relationship between FCLK and MCLK is held correctly, i.e. CPU-

CLK is ignored when SnA = 1. If the FCLK frequency is required to be different from the MEMCLK

frequency, the SnA pin must be held low, and a suitable frequency applied to CPUCLK.

June 1997

ADVANCE DATA BOOK v2.0

CLOCKS, POWER SAVING, AND RESET

191

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