CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

22.4 AC Parameters — List of Timing Figures

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System Reset Timing ........................................................................................ 201

ROM Read Access Timing without Burst Mode (32 Bit) .................................... 203

ROM Read Access Timing, Burst Mode (32 Bit) ............................................... 203

ROM Read Access Timing, Burst Mode (16 Bit) ............................................... 204

ROM Write Access Timing, Burst Mode (32 Bit)................................................ 204

ROM Write Access Timing, Burst Mode (16 Bit)................................................ 205

Fast Page Mode DRAM Read Timing (32 Bit) ................................................... 207

Fast Page Mode DRAM Write Timing (32 Bit) ................................................... 207

EDO DRAM Read Timing (32 Bit) ..................................................................... 208

EDO DRAM Write Timing — Single Word ......................................................... 208

DRAM Memory Refresh Timing......................................................................... 209

8-MHz Simple I/O Read Timing......................................................................... 211

‘Sync’ 8-MHz Simple I/O Read Cycle Timing .................................................... 211

8-MHz Simple I/O Write Timing ......................................................................... 212

‘Sync’ 8-MHz Simple I/O Write Cycle Timing..................................................... 212

8-MHz Module I/O Read Timing ........................................................................ 214

‘Sync’ 8-MHz Module I/O Write Cycle Timing .................................................... 214

16-MHz Type D I/O Write Cycle Timing ............................................................. 216

16-MHz Type D I/O Read Cycle Timing............................................................. 217

16-MHz Type C, B, and A I/O Read Cycle Timing ............................................. 218

16-MHz Type C, B, and A I/O Write Cycle Timing ............................................. 218

16-MHz Type B I/O Read Cycle Timing with PCMCIA....................................... 219

16-MHz Type B /O Write Cycle Timing with PCMCIA ........................................ 220

Keyboard/Mouse Timing.................................................................................... 221

Serial Sound Output Timing (Normal Format) ................................................... 222

Serial Sound Output Timing (Japanese Format) ............................................... 222

Clock Timing with Divide-by-1 Prescalars Selected .......................................... 224

Clock Timing with Divide-by-2 Prescalars Selected .......................................... 224

Video Clock Timing............................................................................................ 224

Sound Clock Timing .......................................................................................... 225

Timing Relationship Between ECLK and ED in LCD Grayscale Mode ............. 225

Timing Relationship Between ECLK and ED in All Other Modes...................... 225

June 1997

ADVANCE DATA BOOK v2.0

ELECTRICAL SPECIFICATIONS

199

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