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CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

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CL-PS7500FE Datasheet PDF : 251 Pages
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CL-PS7500FE
System-on-a-Chip for Internet Appliance
Details of the SUSMODE register (address 0x0320001C) are shown below:
76543210
XXXXXXXS
S
Write
Read
Reset
SUSPEND mode control of external I/O clocks
turn off external I/O clocks when in this mode
0
turn off
1
don't turn off
Enter Suspend mode with MCLK,FCLK,I/O clocks and some internal clocks
stopped. DMA continues and instruction completes on either wake-up event,
nIRQ or nFIQ.
return above value
set to zero
21.2.2 STOP Mode
Entry into STOP mode is achieved by writing to the register location 0x0320002C. Any value can be writ-
ten to the register to enter STOP mode, but the value written appears on the external data bus of the
CL-PS7500FE while the chip is in STOP mode. It is therefore recommended that the value 0xFFFFFFFF
be written to this register as this indicates that both D[31:0] and LA[28:0] are driven high during STOP
mode.
It is very important that all DMA activity is stopped, that all I/O activity is completed, and that the video
subsystem is powered down correctly before the STOP mode register is written to. The OSCPOWER out-
put is controlled by the power management circuitry, and is forced low a short time after the write cycle
begins. This output can be used to disable the external oscillator(s).
Exit from STOP mode can only be achieved by the use of the asynchronous wake-up event pins nEVENT1
and nEVENT2. When either of these is forced low, a sequence of events are triggered that cause the oscil-
lator(s) to be restarted cleanly.
During STOP mode, a zero is driven out from the OSCDELAY pin, ensuring that an external capacitor
forming part of an RC network attached to the OSCDELAY pin remains discharged. As soon as a wake
up event occurs the OSCPOWER pin is set high again, and the open drain OSCDELAY pin is allowed to
float and becomes an input.
At this point, the external capacitor starts to charge, until the schmitt threshold of the OSCDELAY input is
exceeded. From this point, a further two rising edges must be seen on the input clock from the oscillator
before the clock is allowed through to the internal CL-PS7500FE circuitry. The component values used in
the RC circuit should be chosen to ensure that the oscillator has sufficient time to stabilize before
the OSCDELAY input is triggered.
As the video subsystem is inherently dynamic for performance reasons, it is necessary to set it into a spe-
cial Power down mode before STOP mode is entered. To do this, the video Ext register should be pro-
grammed with the data 0xC0000000, the Video Control register should be programmed with the data
0xE00040xx (the last byte depends on the clock source and configuration), and the Sound Control regis-
ter should be programmed with the data 0xB1000000 (if the sound system is configured for use with the
SCLK pin as the clock source. If the sound system is being clocked from the CL-PS7500FE’s internal
32-MHz I/O clock, then the register should be programmed with the value 0xB1000001). These actions
disable the video data path and ensure the entire macrocell is forced into a static state. To ensure that the
194
CLOCKS, POWER SAVING, AND RESET
ADVANCE DATA BOOK v2.0
June 1997

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