CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

NORMAL

SUSPEND

STOP

the default operating condition where all clocks are running and the

chip is functioning normally.

the clocks to the CPU (FCLK and MCLK) are stopped, but all other

parts of the chip remain active so DMA can continue and the display

can continue to be refreshed. It s also possible to stop some of the

external I/O clock outputs to save more power if this can be done safely

without causing problems for I/O peripherals connected to these

clocks.

allows all the clocks to the CL-PS7500FE to be stopped, and the whole

device then draws only leakage currents if all required registers are

appropriately programmed. Outputs are provided from

the CL-PS7500FE to enable the oscillator(s) to be powered down, and

circuitry to allow the oscillator(s) to cleanly restart using an external

RC delay before the clocks inside the CL-PS7500FE are reenabled.

Before STOP mode is entered, a number of registers need to be

programmed appropriately in the video sub-system, and further details

of the full sequence of events required to make most effective use of

the power management features can be found in Section 21.2.2.

21.2.1 SUSPEND Mode

Entry into SUSPEND mode is achieved by writing to the register location 0x0320001C. Any value can be

used, but the value written to bit 0 determines whether the external I/O output clocks CLK16, CLK8,

REF8M and CLK2 are stopped. DMA can continue unaffected, allowing the display and DRAM data to

remain refreshed.

Exit from SUSPEND mode is achieved by a falling edge on either of the asynchronous input event pins,

nEVENT1 and nEVENT2, or by any enabled interrupt source generating a FIQ or IRQ interrupt for the

ARM processor. The assertion of nRESET also causes exit from SUSPEND mode. It is important that the

interrupt mask and enable registers are programmed appropriately before SUSPEND mode is entered if

it is intended that an interrupt source be used to terminate the power saving mode.

The CPU merely sees SUSPEND mode as a write to a location in the memory and I/O register area. It is

unaware of the duration of this write, as both MCLK and FCLK are frozen, and it is a fully static device.

The careful use of SUSPEND mode when no CPU operations are required has a significant effect on the

device‘s average power consumption. It could be used, for example, between key presses while waiting

for more user input. The keyboard controller is still clocked during SUSPEND mode and so is able to gen-

erate interrupts that cause the termination of the write cycle and then cause the CPU to take the interrupt

exception.

June 1997

ADVANCE DATA BOOK v2.0

CLOCKS, POWER SAVING, AND RESET

193

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