DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

Part Name
Description
Manufacturer
CL-PS7500FE Datasheet PDF : 251 Pages
First Prev 51 52 53 54 55 56 57 58 59 60 Next Last
CL-PS7500FE
System-on-a-Chip for Internet Appliance
7. REGISTER DESCRIPTIONS
The CL-PS7500FE supports a variety of operating configurations. Some are controlled by register bits
and are known as the configurations. Other configurations can be controlled by software and are known
as operating modes.
7.1 Register Configuration
The CL-PS7500FE provides three register configuration settings that can be changed while the processor
is running. These are discussed below.
7.1.1 Big and Little Endian (the Bigend Bit)
The Bigend bit in the Control register sets whether the CL-PS7500FE treats words in memory as being
stored in big endian or little endian format. Memory is viewed as a linear collection of bytes numbered
upwards from zero. Bytes 0–3 hold the first stored word; bytes 4–7 the second, and so on.
Little Endian
In the little endian scheme, the lowest-numbered byte in a word is considered to be the least-significant
byte of the word; the highest-numbered byte is the most-significant byte.
In this scheme, byte 0 of the memory system should be connected to D[7:0] (data lines 7 through 0).
HIGHER
ADDRESS
LOWER
ADDRESS
31
24
11
7
3
LITTLE ENDIAN
23
16
10
6
2
15
8
9
5
1
7
0
8
4
0
WORD
ADDRESS
8
4
0
q LEAST-SIGNIFICANT BYTE IS AT LOWEST ADDRESS
q WORD IS ADDRESSED BY BYTE ADDRESS OF LEAST-SIGNIFICANT BYTE
Figure 7-1. Little Endian Addresses of Bytes within Words
52
REGISTER DESCRIPTIONS
ADVANCE DATA BOOK v2.0
June 1997

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]