CL-PS7500FE View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CL-PS7500FE Datasheet PDF : 251 Pages
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CL-PS7500FE
System-on-a-Chip for Internet Appliance
7.3 Registers
The processor macrocell has a total of 37 registers made up of:
q 31 general 32-bit registers
q Six status registers
At any one time, 16 general registers (R0 to R15) and one or two status registers are visible to the pro-
grammer. The visible registers depend on the processor mode, and the other registers (the banked reg-
isters) are switched in to support IRQ, FIQ, Supervisor, Abort, and Undefined mode processing.
The register bank organization is shown in Figure 7-3. The banked registers are shaded.
User32
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15 (PC)
CPSR
General Registers and Program Counter Modes
FIQ32
R0
R1
R2
R3
R4
R5
R6
R7
R8_fiq
R9_fiq
R10_fiq
R11_fiq
R12_fiq
R13_fiq
R14_fiq
R15 (PC)
Supervisor32
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_svc
R14_svc
R15 (PC)
Abort32
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_abt
R14_abt
R15 (PC)
IRQ32
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_irq
R14_irq
R15 (PC)
CPSR
SPSR_fiq
Program Status Registers
CPSR
SPSR_svc
CPSR
SPSR_abt
CPSR
SPSR_irq
Undefined32
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_und
R14_und
R15 (PC)
CPSR
SPSR_und
Figure 7-3. Register Organization
June 1997
ADVANCE DATA BOOK v2.0
55
REGISTER DESCRIPTIONS
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