CL-PS7500FE View Datasheet(PDF) - Cirrus Logic
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CL-PS7500FE Datasheet PDF : 251 Pages
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CL-PS7500FE
System-on-a-Chip for Internet Appliance
26-bit Program Space
When configured for 26-bit program space, the CL-PS7500FE is limited to operating in one of four modes
known as the 26-bit modes. These modes correspond to the modes of the earlier ARM processors and
are known as:
q User26
q FIQ26
q IRQ26
q Supervisor26
NOTE: The PROG32 and DATA32 bits are only used for backward compatibility with earlier ARM processors and
should normally be set to ‘1’. The 32-bit mode is recommended for compatibility with future ARM processors
and all new code should be written to use only the 32-bit operating modes.
Because the original ARM instruction set is modified to accommodate 32-bit operation, there are certain
additional restrictions that programmers must note. The following sections discuss these restrictions.
7.2 Operating Mode Selection
The ARM processor has a 32-bit data bus and a 32-bit address bus. However, only 29 of the address bits
are available at the CL-PS7500FE pins. The data types the processor supports are:
q Bytes (8-bits)
q Words (32-bits) that must be aligned to 4-byte boundaries.
Instructions are exactly one word, and data operations (for example ADD) are only performed on word
quantities. Load and store operations can transfer either bytes or words.
ARM processor supports six modes of operation:
q User mode (usr)
q FIQ mode (fiq)
q IRQ mode (irq)
q Supervisor mode (svc)
q Abort mode (abt)
q Undefined mode (und)
The normal program execution state.
Designed to support a data transfer or channel process.
Used for general-purpose interrupt handling.
A protected mode for the operating system.
Entered after a data or instruction prefetch abort.
Entered when an undefined instruction is executed.
Mode changes can be made under software control or brought about by external interrupts or exception
processing. Most application programs execute in User mode. The other modes, known as Privileged
modes, are entered to service interrupts or exceptions, or to access protected resources.
54
REGISTER DESCRIPTIONS
ADVANCE DATA BOOK v2.0
June 1997
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