MC80F0804D View Datasheet(PDF) - Unspecified
Part Name
Description
Manufacturer
MC80F0804D Datasheet PDF : 120 Pages
| |||
MC80F0704/0708/0804/0808
Example: Make 1ms interrupt using by Timer0 at 4MHz
LDM
LDM
SET1
EI
TM0,#0FH
TDR0,#124
T0E
; divide by 32
; 8us x (124+1)= 1ms
; Enable Timer 0 Interrupt
; Enable Master Interrupt
When
TM0 = 0000 1111B (8-bit Timer mode, Prescaler divide ratio = 32)
TDR0 = 124D = 7CH
fXIN = 4 MHz
INTERRUPT PERIOD =
1
4 × 106 Hz
× 32 × (124+1) = 1 ms
TDR0
7C
~~
0
MATCH
(TDR0 = T0)
7C
7B
up-count
7A
~~
6
5
4
3
2
1
0
Count Pulse
Period
~~
8 μs
Timer 0 (T0IF)
Interrupt
Interrupt period
= 8 μs x (124+1)
Occur interrupt
Occur interrupt
Occur interrupt
TIME
Figure 13-6 Timer Count Example
8-bit Event Counter Mode
In this mode, counting up is started by an external trigger. This
trigger means rising edge of the EC0 or EC1 pin input. Source
clock is used as an internal clock selected with timer mode regis-
ter TM0 or TM2. The contents of timer data register TDRn (n =
0,1,2,3) are compared with the contents of the up-counter Tn. If a
match is found, an timer interrupt request flag TnIF is generated,
and the counter is cleared to “0”. The counter is restart and count
up continuously by every rising edge of the EC0 or EC1 pin input.
The maximum frequency applied to the EC0 or EC1 pin is fXIN/
2 [Hz].
In order to use event counter function, the bit 4, 5 of the Port Se-
lection Register PSR0(address 0F8H) is required to be set to “1”.
After reset, the value of timer data register TDRn is initialized to
"0", The interval period of Timer is calculated as below equation.
Period (sec) = f---X-1--I--N-- × 2 × Divide Ratio × (TDRn+1)
Start count
EC0 pin input
Up-counter
TDR0
T1IF interrupt
0
1
2
n
n-1 n 0
1
2
Figure 13-7 Event Counter Mode Timing Chart
56
October 31, 2011 Ver 1.03
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