MC80F0704/0708/0804/0808
TM2
7
6
5
4
3
2
1
0
-
- CAP2 T2CK2 TB2TCCKL1 T2CK0 T2CN T2ST
-
-
0
XX
XX
X
ADDRESS: 0D6H
INITIAL VALUE: --000000B
X means don’t care
TM3
7
6
5
4
3
2
1
0
POL 16BIT PWM3E CAP3 TB3TCCKL1 T3CK0 T3CN T3ST
X1
0
0
1
1
X
X
ADDRESS: 0D8H
INITIAL VALUE: 00H
X means don’t care
EC1 PIN
XIN PIN
EDGE
DETECTOR
T2CK[2:0]
111
÷2
000
÷4
001
÷8
010
÷ 16 011
÷ 64
100
÷ 256
101
÷ 1024 110
MUX
T2CN
TIMER 2 + TIMER 3 → TIMER 2 (16-bit)
T2ST
0: Stop
1: Clear and start
T3 + T2
(16-bit)
clear
Comparator
TDR3 + TDR2
(16-bit)
Higher byte Lower byte
COMPARE DATA
T2IF
TIMER 2
INTERRUPT
(Not Timer 3 interrupt)
Figure 13-10 16-bit Timer/Counter for Timer 2, 3
13.3 8-bit Compare Output (16-bit)
The MC80F0704/0708/0804/0808 has Timer Compare Output
function. To pulse out, the timer match can goes to port pin (T0O
or T2O) as shown in Figure 13-3 or Figure 13-4 . Thus, pulse out
is generated by the timer match. These operation is implemented
to pin, R05/AN5//T0O or R06/AN6/T2O.
In this mode, the bit T0OE or T2OE bit of Port Selection register1
(PSR1.0 or PSR1.1) should be set to "1". This pin output the sig-
nal having a 50 : 50 duty square wave, and output frequency is
same as below equation.
fCOMP = -2-----×----P----r-O--e--s-s--c--c--i-al--l-l-a-e--t-r-i--o--V--n--a---F-l-u--r--ee----q-×--u---(-e-T--n---D-c---y-R-----+-----1----)-
13.4 8-bit Capture Mode
The Timer 0 capture mode is set by bit CAP0 of timer mode reg-
ister TM0 (bit CAP1 of timer mode register TM1 for Timer 1) as
shown in Figure 13-11 . Likewise, the Timer 2 capture mode is
set by bit CAP2 of timer mode register TM2 (bit CAP3 of timer
mode register TM3 for Timer 3) as shown in Figure 13-12 .
The Timer/Counter register is increased in response internal or
external input. This counting function is same with normal timer
mode, and Timer interrupt is generated when timer register T0
(T1, T2, T3) increases and matches TDR0 (TDR1, TDR2,
TDR3).
This timer interrupt in capture mode is very useful when the pulse
width of captured signal is more wider than the maximum period
October 31, 2011 Ver 1.03
59