MC80F0704/0708/0804/0808
of Timer.
For example, in Figure 13-14 , the pulse width of captured signal
is wider than the timer data value (FFH) over 2 times. When ex-
ternal interrupt is occurred, the captured value (13H) is more little
than wanted value. It can be obtained correct value by counting
the number of timer overflow occurrence.
Timer/Counter still does the above, but with the added feature
that a edge transition at external input INTx pin causes the current
value in the Timer x register (T0,T1,T2,T3), to be captured into
registers CDRx (CDR0, CDR1, CDR2, CDR3), respectively. Af-
ter captured, Timer x register is cleared and restarts by hardware.
It has three transition modes: "falling edge", "rising edge", "both
edge" which are selected by interrupt edge selection register
IEDS. Refer to “17.4 External Interrupt” on page 85. In addition,
the transition at INTn pin generate an interrupt.
Note: The CDRn and TDRn are in same address.In the capture
mode, reading operation is read the CDRn, not TDRn because
path is opened to the CDRn.
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October 31, 2011 Ver 1.03