MC80F0804D View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

MC80F0804D

8-BIT SINGLE-CHIP MICROCONTROLLERS

Unspecified 

MC80F0704/0708/0804/0808

13.6 PWM Mode

The MC80F0704/0708/0804/0808 has high speed PWM (Pulse

Width Modulation) functions which shared with Timer1 or

Timer3.

In PWM mode, R10 / PWM1O or R11 / PWM3O pin output up

to a 10-bit resolution PWM output. These pins should be config-

ured as a PWM output by setting "1" bit PWM1OE and

PWM3OE in PSR0 register.

The period of the PWM1 output is determined by the T1PPR (T1

PWM Period Register) and T1PWHR[3:2] (bit3,2 of T1 PWM

High Register) and the duty of the PWM output is determined by

the T1PDR (T1 PWM Duty Register) and T3PWHR[1:0] (bit1,0

of T1 PWM High Register).

The period of the PWM3 output is determined by the T3PPR (T3

PWM Period Register) and T3PWHR[3:2] (bit3,2 of T3 PWM

High Register) and the duty of the PWM output is determined by

the T3PDR (T3 PWM Duty Register) and T3PWHR[1:0] (bit1,0

of T3 PWM High Register).

The user writes the lower 8-bit period value to the T1(3)PPR and

the higher 2-bit period value to the T1(3)PWHR[3:2]. And writes

duty value to the T1(3)PDR and the T1(3)PWHR[1:0] same way.

The T1(3)PDR is configured as a double buffering for glitchless

PWM output. In Figure 13-18 , the duty data is transferred from

the master to the slave when the period data matched to the count-

ed value. (i.e. at the beginning of next duty cycle)

PWM1(3) Period = [PWM1(3)HR[3:2]T(2)3PPR] X

Source Clock

PWM1(3) Duty = [PWM1(3)HR[1:0]T3PDR] X Source

Clock

The relation of frequency and resolution is in inverse proportion.

Table 13-3 shows the relation of PWM frequency vs. resolution.

If it needed more higher frequency of PWM, it should be reduced

resolution.

Frequency

Resolution T1CK[1:0] T1CK[1:0]

= 00(250nS) = 01(500nS)

10-bit

3.9kHz

0.98kHz

9-bit

7.8kHz

1.95kHz

8-bit

15.6kHz

3.90kHz

7-bit

31.2kHz

7.81kHz

T1CK[1:0]

= 10(2uS)

0.49kHz

0.97kHz

1.95kHz

3.90kHz

Table 13-3 PWM Frequency vs. Resolution at 4MHz

The bit POL of TM1 or TM3 decides the polarity of duty cycle.

If the duty value is set same to the period value, the PWM output

is determined by the bit POL (1: High, 0: Low). And if the duty

value is set to "00H", the PWM output is determined by the bit

POL (1: Low, 0: High).

It can be changed duty value when the PWM output. However the

changed duty value is output after the current period is over. And

it can be maintained the duty value at present output when

changed only period value shown as Figure 13-20 . As it were, the

absolute duty time is not changed in varying frequency. But the

changed period value must greater than the duty value.

Note: If changing the Timer1 to PWM function, it should be stop

the timer clock firstly, and then set period and duty register value.

If user writes register values while timer is in operation, these reg-

ister could be set with certain values.

Ex) Sample Program @4MHz 2uS

LDM

LDM

LDM

LDM

LDM

TM1,#1010_1000b ; Set Clock & PWM3E

T1PPR,#199

; Period :400uS=2uSX(199+1)

T1PDR,#99

; Duty:200uS=2uSX(99+1)

PWM1HR,00H

TM1,#1010_1011b ; Start timer1

66

October 31, 2011 Ver 1.03

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