MC80F0804D View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

MC80F0804D

8-BIT SINGLE-CHIP MICROCONTROLLERS

Unspecified 

MC80F0704/0708/0804/0808

Serial I/O Mode Register (SIOM) controls serial I/O function.

According to SCK1 and SCK0, the internal clock or external

clock can be selected.

Serial I/O Data Register (SIOR) is an 8-bit shift register. First

LSB is send or is received first.

SIOM

SIOR

R/W R/W R/W R/W R/W R/W R/W R

7

6

5

4

3

2

1

0

POL IOSW SM1 SM0 BSTCCKL1 SCK0 SIOST SIOSF

ADDRESS: 0E2H

INITIAL VALUE: 0000 0001B

Serial transmission status bit

0: Serial transmission is in progress

1: Serial transmission is completed

Serial transmission start bit

Setting this bit starts an Serial transmission.

After one cycle, bit is cleared to “0” by hardware.

Serial transmission Clock selection

00: fXIN ÷ 4

01: fXIN ÷ 16

10: TMR0OV(Timer0 Overflow)

11: External Clock

Serial transmission Operation Mode

00: Normal Port (R00,R01,R02)

01: Sending Mode (SCK,R01,SO)

10: Receiving Mode (SCK,SI,R02)

11: Sending & Receiving Mode (SCK,SI,SO)

Serial Input Pin Selection bit

0: SI Pin Selection

1: SO Pin Selection

R/W R/W R/W R/W R/W R/W R/W R/W

76543210

BTCL

Serial Clock Polarity Selection bit

0: Data Transmission at Falling Edge

Received Data Latch at Rising Edge

1: Data Transmission at Rising Edge

Received Data Latch at Falling Edge

ADDRESS: 0E3H

INITIAL VALUE: Undefined

Sending Data at Sending Mode

Receiving Data at Receiving Mode

Figure 15-2 SIO Control Register

15.1 Transmission/Receiving Timing

The serial transmission is started by setting SIOST(bit1 of SIOM)

to “1”. After one cycle of SCK, SIOST and SIOSF (bit 0 of SI-

OM) is cleared automatically to “0”. At the default state of POL

bit clear, the serial output data from 8-bit shift register is output

at falling edge of SCLK, and input data is latched at rising edge

of SCLK pin (Refer to Figure 15-3 ). When transmission clock is

counted 8 times, serial I/O counter is cleared as ‘0”. Transmission

clock is halted in “H” state and serial I/O interrupt (SIOIF) oc-

curred. SIOSF is set to “1” automatically.

74

October 31, 2011 Ver 1.03

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