MC80F0804D View Datasheet(PDF) - Unspecified
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MC80F0804D Datasheet PDF : 120 Pages
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MC80F0704/0708/0804/0808
17. INTERRUPTS
The MC80F0704/0708/0804/0808 interrupt circuits consist of In-
terrupt enable register (IENH, IENL), Interrupt request flags of
IRQH, IRQL, Priority circuit, and Master enable flag (“I” flag of
PSW). Fifteen interrupt sources are provided. The configuration
of interrupt circuit is shown in Figure 17-1 and interrupt priority
is shown in Table 17-1.
The External Interrupts INT0 ~ INT3 each can be transition-acti-
vated (1-to-0 or 0-to-1 transition) by selection IEDS register.
The flags that actually generate these interrupts are bit INT0IF,
INT1IF, INT2IF and INT3IF in register IRQH. When an external
interrupt is generated, the generated flag is cleared by the hard-
ware when the service routine is vectored to only if the interrupt
was transition-activated.
The Timer 0 ~ Timer 3 Interrupts are generated by T0IF, T1IF,
T2IF and T3IF which is set by a match in their respective timer/
counter register.
The Basic Interval Timer Interrupt is generated by BITIF which
is set by an overflow in the timer register.
The AD converter Interrupt is generated by ADCIF which is set
by finishing the analog to digital conversion.
The Watchdog timer is generated by WDTIF and WTIF which is
set by a match in Watchdog timer register.
INT0
INT1
INT2
INT3
Serial
Communication
Timer 0
Timer 1
Timer 2
Timer 3
A/D Converter
Watchdog Timer
BIT
Internal bus line
IRQH
[0ECH]
INT0IF
INT1IF
INT2IF
INT3IF
[0EAH]
IENH
Interrupt Enable
Register (Higher byte)
SIOIF
T0IF
IRQL
[0EDH]
T1IF
T2IF
T3IF
I-flag is in PSW, it is cleared by “DI”, set by
“EI” instruction. When it goes interrupt service,
I-flag is cleared by hardware, thus any other
interrupt are inhibited. When interrupt service is
completed by “RETI” instruction, I-flag is set to
“1” by hardware.
Release STOP/SLEEP
I-flag
Interrupt Master
Enable Flag
Interrupt
Vector
Address
Generator
To CPU
ADCIF
WDTIF
BITIF
[0EBH]
IENL
Interrupt Enable
Register (Lower byte)
Internal bus line
Figure 17-1 Block Diagram of Interrupt
The Basic Interval Timer Interrupt is generated by BITIF which
is set by a overflow in the timer counter register.
October 31, 2011 Ver 1.03
79
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