MC80F0804D View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

MC80F0804D

8-BIT SINGLE-CHIP MICROCONTROLLERS

Unspecified 

MC80F0704/0708/0804/0808

Figure 17-3 Interrupt Request Flag Register

17.1 Interrupt Sequence

An interrupt request is held until the interrupt is accepted or the

interrupt latch is cleared to “0” by a reset or an instruction. Inter-

rupt acceptance sequence requires 8 cycles of fXIN (2μs at fX-

IN=4MHz) after the completion of the current instruction

execution. The interrupt service task is terminated upon execu-

tion of an interrupt return instruction [RETI].

Interrupt acceptance

1. The interrupt master enable flag (I-flag) is cleared to

“0” to temporarily disable the acceptance of any follow-

ing maskable interrupts. When a non-maskable inter-

rupt is accepted, the acceptance of any following

interrupts is temporarily disabled.

2. The contents of the program counter (return address)

and the program status word are saved (pushed) onto the

stack area. The stack pointer decreases 3 times.

3. The entry address of the interrupt service program is

read from the vector table address and the entry address

is loaded to the program counter.

4. The instruction stored at the entry address of the inter-

rupt service program is executed.

System clock

Instruction Fetch

Address Bus

PC

SP SP-1

SP-2

V.L. V.H.

New PC

Data Bus

Not used

PCH PCL PSW V.L. ADL ADH

OP code

Internal Read

Internal Write

Interrupt Processing Step

Interrupt Service Task

V.L. and V.H. are vector addresses.

ADL and ADH are start addresses of interrupt service routine as vector contents.

Figure 17-4 Timing chart of Interrupt Acceptance and Interrupt Return Instruction

Basic Interval Timer

Vector Table Address

Entry Address

A interrupt request is not accepted until the I-flag is set to “1”

even if a requested interrupt has higher priority than that of the

current interrupt being serviced.

0FFE0H

0FFE1H

012H

0E3H

0E312H

0EH

0E313H

2EH

When nested interrupt service is required, the I-flag should be set

to “1” by “EI” instruction in the interrupt service program. In this

case, acceptable interrupt sources are selectively enabled by the

individual interrupt enable flags.

Correspondence between vector table address for BIT interrupt

and the entry address of the interrupt service program.

Clearing Interrupt Request Flag

The Interrupt Request flag may not cleared itself during interrupt

acceptance processing. After interrupt acceptance, it should be

cleared as shown in interrupt service routine.

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October 31, 2011 Ver 1.03

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