MC80F0804D View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

MC80F0804D

8-BIT SINGLE-CHIP MICROCONTROLLERS

Unspecified 

MC80F0704/0708/0804/0808

18. POWER SAVING OPERATION

The MC80F0704/0708/0804/0808 has two power-down modes.

In power-down mode, power consumption is reduced

considerably. For applications where power consumption is a

critical factor, device provides two kinds of power saving func-

18.1 Sleep Mode

In this mode, the internal oscillation circuits remain active.

Oscillation continues and peripherals are operate normally but

CPU stops. Movement of all peripherals is shown in Table 18-1.

SLEEP mode is entered by setting the SSCR register to “0Fh”. It

tions, STOP mode and SLEEP mode. Table 18-1 shows the status

of each Power Saving Mode. SLEEP mode is entered by the

SSCR register to “0Fh”., and STOP mode is entered by STOP in-

struction after the SSCR register to “5Ah”.

is released by Reset or interrupt. To be released by interrupt, in-

terrupt should be enabled before SLEEP mode.

SSCR

WW WWWW WW

7

6

5

4

3

2

1

0

ADDRESS: 0F5H

INITIAL VALUE: 0000 0000B

Power Down Control

5AH: STOP mode

0FH: SLEEP mode

NOTE :

To get into STOP mode, SSCR must be set to 5AH just before STOP instruction execution.

At STOP mode, Stop & Sleep Control Register (SSCR) value is cleared automatically when released.

To get into SLEEP mode, SSCR must be set to 0FH.

Figure 18-1 STOP and SLEEP Control Register

Release the SLEEP mode

The exit from SLEEP mode is hardware reset or all interrupts.

Reset re-defines all the Control registers but does not change the

on-chip RAM. Interrupts allow both on-chip RAM and Control

registers to retain their values.

If I-flag = 1, the normal interrupt response takes place. If I-flag =

0, the chip will resume execution starting with the instruction fol-

lowing the SLEEP instruction. It will not vector to interrupt ser-

vice routine. (refer to Figure 18-4 )

When exit from SLEEP mode by reset, enough oscillation stabi-

lizing time is required to normal operation. Figure 18-3 shows

the timing diagram. When released from the SLEEP mode, the

Basic interval timer is activated on wake-up. It is increased from

00H until FFH. The count overflow is set to start normal opera-

tion. Therefore, before SLEEP instruction, user must be set its

relevant prescaler divide ratio to have long enough time (more

than 20msec). This guarantees that oscillator has started and sta-

bilized. By interrupts, exit from SLEEP mode is shown in Figure

18-2 . By reset, exit from SLEEP mode is shown in Figure 18-3 .

October 31, 2011 Ver 1.03

87

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