MC80F0804D View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

MC80F0804D

8-BIT SINGLE-CHIP MICROCONTROLLERS

Unspecified 

MC80F0704/0708/0804/0808

Note: After STOP instruction, at least two or more NOP instruc-

tion should be written.

Ex)

LDM CKCTLR,#0FH ;more than 20ms

LDM SSCR,#5AH

STOP

NOP ;for stabilization time

NOP ;for stabilization time

In the STOP operation, the dissipation of the power associated

with the oscillator and the internal hardware is lowered; however,

the power dissipation associated with the pin interface (depend-

ing on the external circuitry and program) is not directly deter-

mined by the hardware operation of the STOP feature. This point

should be little current flows when the input level is stable at the

power voltage level (VDD/VSS); however, when the input level

gets higher than the power voltage level (by approximately 0.3 to

0.5V), a current begins to flow. Therefore, if cutting off the out-

put transistor at an I/O port puts the pin signal into the high-im-

pedance state, a current flow across the ports input transistor,

requiring to fix the level by pull-up or other means.

Peripheral

CPU

RAM

Basic Interval Timer

Watchdog Timer

Timer/Counter

Buzzer, ADC

SIO

Oscillator

I/O Ports

Control Registers

Internal Circuit

Prescaler

Address Data Bus

Release Source

STOP Mode

Stop

Retain

Halted

Stop (Only operates in RC-WDT mode)

Halted (Only when the event counter mode

is enabled, timer operates normally)

Stop

Only operate with external clock

Stop (XIN=L, XOUT=H)

Retain

Retain

Stop mode

Retain

Retain

Reset, Timer(EC0,1), SIO (ext. clock),

Watchdog Timer (RC-WDT mode),

External Interrupt

SLEEP Mode

Stop

Retain

Operates Continuously

Stop

Operates Continuously

Stop

Only operate with external clock

Oscillation

Retain

Retain

Sleep mode

Active

Retain

Reset, All Interrupts

Table 18-1 Peripheral Operation During Power Saving Mode

Release the STOP mode

The source for exit from STOP mode is hardware reset, external

interrupt, Timer(EC0,1), WDT, SIO. When releasing from the

STOP mode by the SIO(ext.clock), the SIOR has dummy data

and the SIOST bit should be cleared after release from the STOP

mode.

Reset re-defines all the Control registers but does not change the

on-chip RAM. External interrupts allow both on-chip RAM and

Control registers to retain their values.

If I-flag = 1, the normal interrupt response takes place. If I-flag =

0, the chip will resume execution starting with the instruction fol-

lowing the STOP instruction. It will not vector to interrupt service

routine. (refer to Figure 18-4 )

When exit from Stop mode by external interrupt, enough oscilla-

tion stabilizing time is required to normal operation. Figure 18-5

shows the timing diagram. When released from the Stop mode,

the Basic interval timer is activated on wake-up. It is increased

from 00H until FFH. The count overflow is set to start normal op-

eration. Therefore, before STOP instruction, user must be set its

relevant prescaler divide ratio to have long enough time (more

than 20msec). This guarantees that oscillator has started and sta-

bilized.

By reset, exit from Stop mode is shown in Figure 18-6 .

October 31, 2011 Ver 1.03

89

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