MC80F0804D View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

MC80F0804D

8-BIT SINGLE-CHIP MICROCONTROLLERS

Unspecified 

MC80F0704/0708/0804/0808

Oscillator

(XI pin)

STOP Mode

Internal

Clock

RESET

Internal

RESET

STOP Instruction Execution

Time can not be control by software

Stabilization Time

tST = 65.5mS @4MHz

Figure 18-6 Timing of STOP Mode Release by Reset

18.3 Stop Mode at Internal RC-Oscillated Watchdog Timer Mode

In the Internal RC-Oscillated Watchdog Timer mode, the on-chip

oscillator is stopped. But internal RC oscillation circuit is oscil-

lated in this mode. The on-chip RAM and Control registers are

held. The port pins out the values held by their respective port

data register, port direction registers.

The Internal RC-Oscillated Watchdog Timer mode is activated

by execution of STOP instruction after setting the bit RCWDT of

CKCTLR to "1". (This register should be written by byte opera-

tion. If this register is set by bit manipulation instruction, for ex-

ample "set1" or "clr1" instruction, it may be undesired operation)

Note: Caution: After STOP instruction, at least two or more NOP

instruction should be written

Ex)

LDM WDTR,#1111_1111B

LDM CKCTLR,#0010_1110B

LDM SSCR,#0101_1010B

STOP

NOP ;for stabilization time

NOP ;for stabilization time

The exit from Internal RC-Oscillated Watchdog Timer mode is

hardware reset or external interrupt or watchdog timer interrupt

(at RC-watchdog timer mode). Reset re-defines all the Control

registers but does not change the on-chip RAM. External inter-

rupts allow both on-chip RAM and Control registers to retain

their values.

If I-flag = 1, the normal interrupt response takes place. In this

case, if the bit WDTON of CKCTLR is set to "0" and the bit

WDTE of IENH is set to "1", the device will execute the watch-

dog timer interrupt service routine(Figure 8-6 ). However, if the

bit WDTON of CKCTLR is set to "1", the device will generate

the internal Reset signal and execute the reset processing(Figure

18-8 ). If I-flag = 0, the chip will resume execution starting with

the instruction following the STOP instruction. It will not vector

to interrupt service routine.(refer to Figure 18-4 )

When exit from Stop mode at Internal RC-Oscillated Watchdog

Timer mode by external interrupt, the oscillation stabilization

time is required to normal operation. Figure 18-7 shows the tim-

ing diagram. When release the Internal RC-Oscillated Watchdog

Timer mode, the basic interval timer is activated on wake-up. It

is increased from 00H until FFH. The count overflow is set to start

normal operation. Therefore, before STOP instruction, user must

be set its relevant prescaler divide ratio to have long enough time

(more than 20msec). This guarantees that oscillator has started

and stabilized. By reset, exit from internal RC-Oscillated Watch-

dog Timer mode is shown in Figure 18-8 .

October 31, 2011 Ver 1.03

91

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