FDC37B80X View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
Manufacturer
FDC37B80X
SMSC -> Microchip
FDC37B80X Datasheet PDF : 194 Pages
| |||
PDATA<7:0>
nACK
nAUTOFD
t2
t1
t5
t6
t4
t3
t4
FIGURE 18 - ECP PARALLEL PORT REVERSE TIMING
NAME
DESCRIPTION
t1 PDATA Valid to nACK Asserted
t2 nAUTOFD Deasserted to PDATA Changed
t3 nACK Asserted to nAUTOFD Deasserted
(Notes 1,2)
t4 nACK Deasserted to nAUTOFD Asserted (Note 2)
t5 nAUTOFD Asserted to nACK Asserted
t6 nAUTOFD Deasserted to nACK Deasserted
MIN TYP MAX UNITS
0
ns
0
ns
80
200
ns
80
200
ns
0
ns
0
ns
Note 1: Maximum value only applies if there is room in the FIFO and terminal count has not been
received. ECP can stall by keeping nAUTOFD low.
Note 2: nACK is not considered asserted or deasserted until it is stable for a minimum of 75 to 130
ns.
187
Share Link: 