FDC37C932APM View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

FDC37C932APM

Plug and Play Compatible Ultra I/O™ Controller with Soft Power Management

SMSC -> Microchip 

Table 106 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08]

NAME

REG INDEX

DEFINITION

STATE

WDT_CFG

Default = 0x00

on Vcc POR or

Reset_Drv

0xF3 Watchdog Timer Configuration

C

Bit[0] Joy-stick Enable

=1 WDT is reset upon an I/O read or write of the

Game Port

=0 WDT is not affected by I/O reads or writes to the

Game Port.

Bit[1] Keyboard Enable

=1 WDT is reset upon a keyboard interrupt.

=0 WDT is not affected by keyboard interrupts.

Bit[2] Mouse Enable

=1 WDT is reset upon a mouse interrupt

=0 WDT is not affected by mouse interrupts.

Bit[3] PWRLED Timeout enable

=1 Enables the Power LED to toggle at a 1Hz rate

with 50 percent duty cycle while the Watch-

dog Status bit is set.

=0 Disables the Power LED toggle during Watch-dog

timeout status.

Bit[7:4] WDT Interrupt Mapping

1111 = IRQ15

.........

0011 = IRQ3

0010 = Invalid

0001 = IRQ1

0000 = Disable

WDT_CTRL

Default = 0x00

Cleared by VTR

POR

0xF4 Watchdog Timer Control

C

Bit[0] Watch-dog Status Bit, R/W

=1 WD timeout occured

=0 WD timer counting

Bit[1] Power LED Toggle Enable, R/W

=1 Toggle Power LED at 1Hz rate with 50 percent

duty cycle. (1/2 sec. on, 1/2 sec. off)

=0 Disable Power LED Toggle

Bit[2] Force Timeout, W

=1 Forces WD timeout event; this bit is self-clearing

Bit[3] P20 Force Timeout Enable, R/W

= 1 Allows rising edge of P20, from the keyboard

controller, to force the WD timeout event. A

WD timeout event may still be forced by

setting the Force Timeout Bit, bit 2.

= 0 P20 activity does not generate the WD timeout

event.

235

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