FDC37C932APM View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

FDC37C932APM

Plug and Play Compatible Ultra I/O™ Controller with Soft Power Management

SMSC -> Microchip 

Table 106 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08]

NAME

REG INDEX

DEFINITION

STATE

The P20 signal will remain high for a minimum of

1us and can remain high indefinitely. Therefore,

when P20 forced timeouts are enabled, a self-

clearing edge-detect circuit is used to generate a

signal which is ORed with the signal generated by

the Force Timeout Bit.

Bit[4] Reserved. Set to 0

Bit[5] Stop_Cnt: This is used to terminate Delay 2

(Note 1) without generating a power own.

This is used if the software determines that

the power down should be aborted. When

read, this bit indicates the following:

Stop_Cnt = 0; Counter running Stop_Cnt =

1; Counter Stopped. Note: The write is self

clearing.

Bit[6] Restart_Cnt: This is used to restart Delay 2

(Note 1) from the button input to the

generation of the power down. When

restarted, the count will start over and delay

the power down for the time that Delay 2 is

set for (Default=500msec). The software

can continue to do this indefinately with out

allowing a powerdown. This bit is self

clearing. 1=Restart; Automatically cleared.

Bit[7] SPOFF: This is used to force a software power

down. This bit is self clearing.

Note 1: This delay is programmable via the Delay 2

Time Set Register at Logical Device 8, 0xB8.

GP1

Default = 0x00

on VCC POR or

Reset_Drv

GP2

Default = 0x00

on VCC POR or

Reset_Drv

GP4

Default = 0x00

on VCC POR or

Reset_Drv

0xF6 Refer to Table 49 for Bit Definitions.

0xF7 Refer to Table 49 for Bit Definitions.

0xF8 Refer to Table 49 for Bit Definitions.

236

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