ST10F163 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST10F163

16-BIT MCU WITH 128KBYTE FLASH MEMORY

STMicroelectronics 

ST10F163

MOV

MOV

MOV

SCXT

R1, #09000h

R2, #09FFEh

R3, #01000h

DPP2,#0Ch

MOV

R4, #050d

MOV

R7, #08000h

#define FCR 08000h

EXTS

#1, #2

MOV

FCR, R7

MOV

[R7], R7

NOP

NOP

POP

DPP2

; First Flash Segment Offset Address

; Last Flash Segment Offset Address

; Source data address: use DPP2 as

; data page pointer

; Source is in page 12 (0Ch): save previous

; DPP2 value and load it with source page

; number

; 50ns is 20 MHz CPU clock frequency

; R7 used for Flash trigger sequence

; flash can be mapped in segment 0 or 1

; first part

; second part

; WARNING: place 2 NOP operations after

; the Unlock sequence to avoid all possible

; pipeline conflict in STEAK programs

; restore DPP2

V.2 - Flash memory configuration

The default memory configuration is determined

by the state of the EA pin at reset. This value is

stored in the Internal ROM enable bit: ROMEN of

the SYSCON Register.

When ROMEN=0, the internal ROM is disabled

and external ROM is used for start-up control. The

first 32KBytes of the flash memory area must be

re-mapped to segment 1, to enable their later use.

This is done by setting the ROMS1 bit of

SYSCON to 0. This is done by the externally sup-

plied program, before the execution of the EINIT

instruction.

If program execution starts from external memory,

but access to the flash memory (re-mapped to

Bank 1) is required later, one of the following val-

ues has to be written to the SYSCON register,

before the end of initialization:

– If flash is to be mapped to segment 1:

xxx100xxxxxxxxxxb

(ROMS1=1,SGTDIS=0)

– If flash is to be mapped to segment 0:

xxx000xxxxxxxxxxb

(ROMS1=0,SGTDIS=0)

All other parts of the flash memory (addresses

18000h - 1FFFFh) remain unaffected.

The SGTDIS Segmentation Disable/Enable must

be set to 0 so that the 64KBytes of on-chip mem-

ory can be used in addition to the external boot

memory. The correct procedure for changing the

segmentation registers must be observed, to pre-

vent unwanted trap conditions:

– Instructions that configure the internal memory

must only be executed from external memory

or from the internal RAM.

– Whenever the internal memory is disabled, ena-

bled or re-mapped, the DPPs must be explicitly

(re)loaded to enable correct data accesses to

the internal memory and/or external memory.

V.3 - Flash protection

The flash protection mode, prevents the reading

of data operands in the flash memory by anything

but a program executed from the flash memory

itself. Flash protection mode permits program

branches from, or into the flash memory, but does

not permit erasing and programming of the flash

memory.

Flash protection is controlled by the Protection

UPROM Programming Bit (UPROG). UPROG is a

’hidden’ one-time programmable bit. It is only

accessible in a special mode, entered, for exam-

ple, via a flash EPROM programming board. If

UPROG is set to ‘1’, flash protection is active after

reset. By default flash protection is disabled

(UPROG=0).

For deactivation of flash protection, where the

flash memory has to be reprogrammed with

updated program/variables, a zero value must be

written at every even address in the active

address space of the flash memory. This write can

only be done by an instruction executed from the

internal flash memory itself, e.g. MOV

FLASH,ZEROS.

14/58

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