ST10F163
Table 6 : List of possible interrupt sources, flags, vector and trap numbers (continued)
Source of Interrupt or PEC
Service Request
Request
Flag
Enable
Flag
Interrupt
Vector
Vector
Location
Trap
Number
SSP Interrupt
XP1IR
XP1IE
XP1INT
00’0104h
41h
PLL Unlock / OWD
XP3IR
XP3IE
XP3INT
00’010Ch
43h
The ST10F163 provides an excellent mechanism
to identify and to process exceptions or error con-
ditions that arise during run-time, called‘Hardware
Traps’.
Hardware traps cause an immediate
non-maskable system reaction which is similar to
a standard interrupt service (branching to a dedi-
cated vector table location). The occurrence of a
hardware trap is additionally signified by an indi-
vidual bit in the trap flag register (TFR). Except
when another higher prioritized trap service is in
progress, a hardware trap will interrupt any actual
program execution. In turn, hardware trap ser-
vices can normally not be interrupted by standard
or PEC interrupts.
Table 7 shows all of the possible exceptions or
error conditions that can arise during run time.
Table 7 : Exceptions or error conditions that can arise during run-time
Exception Conditio n
Trap
Flag
Trap
Vector
Vector
Location
Trap
Number
Trap
Priority
Reset Functions:
Hardware Reset
Software Reset
Watchdog Timer Overflow
Class A Hardware Traps:
Non-Maskable Interrupt
Stack Overflow
Stack Underflow
Class B Hardware Traps:
Undefined Opcode
Protected Instruction Fault
Illegal Word Operand Access
Illegal Instruction Access
Illegal External Bus Access
Reserved
Software Traps:
TRAP Instruction
RESET
00’0000h
00h
III
RESET
00’0000h
00h
III
RESET
00’0000h
00h
III
NMI
NMITRAP
00’0008h
02h
II
STKOF
STOTR AP
00’0010h
04h
II
STKUF
STUTRAP
00’0018h
06h
II
UNDOPC
PRTFLT
ILLOPA
ILLINA
ILLBUS
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
00’0028h
00’0028h
00’0028h
00’0028h
00’0028h
[2Ch –3Ch]
Any
[00’0000h–
00’01FCh]
in steps of 4h
0Ah
0Ah
0Ah
0Ah
0Ah
[0Bh – 0Fh]
Any
[00h – 7Fh]
I
I
I
I
I
Current
CPU
Priority
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