ST10F163 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST10F163

16-BIT MCU WITH 128KBYTE FLASH MEMORY

STMicroelectronics 

ST10F163

VI - EXTERNAL BUS CONTROLLER

All of the external memory accesses are per-

formed by a particular on-chip External Bus Con-

troller (EBC). It can be programmed either to

Single Chip Mode when no external memory is

required, or to one of four different external mem-

ory access modes:

– 16-/18-/20-/24-bit Addresses, 16-bit Data, De-

multiplexed

– 16-/18-/20-/24-bit Addresses, 16-bit Data, Multi-

plexed

– 16-/18-/20-/24-bit Addresses, 8-bit Data, Multi-

plexed

– 16-/18-/20-/24-bit Addresses, 8-bit Data, De-

multiplexed

In the demultiplexed bus modes, addresses are

output on PORT1 and data is input/output on

PORT0 or P0L, respectively. In the multiplexed

bus modes both addresses and data use PORT0

for input/output.

Important timing characteristics of the external

bus interface (Memory Cycle Time, Memory

Tri-State Time, Length of ALE and Read Write

Delay) have been made programmable. This

gives the choice of a wide range of different types

of memories and external peripherals. In addition,

up to 4 independent address windows may be

defined (via register pairs ADDRSELx / BUS-

CONx).

This gives access to different resources with dif-

ferent bus characteristics. These address win-

dows are arranged hierarchically where

BUSCON4 overrides BUSCON3 and BUSCON2

overrides BUSCON1.

All accesses to locations not covered by these 4

address windows are controlled by BUSCON0.

Up to 5 external CS signals (4 windows plus

default) can be generated in order to save external

glue logic. Access to very slow memories is sup-

ported via a particular ‘Ready’ function.

A HOLD/HLDA protocol is available for bus arbi-

tration so that external resources can be shared

with other bus masters. The bus arbitration is

enabled by setting bit HLDEN in register

SYSCON. After setting HLDEN once, pins

P6.7...P6.5 (BREQ, HLDA, HOLD) are automati-

cally controlled by the EBC. In Master Mode

(default after reset) the HLDA pin is an output.

By setting bit DP6.7 to’1’ the Slave Mode is

selected where pin HLDA is switched to input.

This allows to directly connect the slave controller

to another master controller without glue logic.

For applications which require less than 16

MBytes of external memory space, this address

space can be restricted to 1 MByte, 256 KByte or

to 64 KByte. In this case Port 4 outputs four, two

or no address lines at all. If an address space of

16 MBytes is used, it outputs all 8 address lines.

Note

When the on-chip SSP Module is to be used the segment

address output on Port 4 must be limi ted to 4 bits (i.e.

A19...A16) in order to enable the alternate function of the

SSP interface pins.

VI.1 - Programmable chip select timing control

The position of the CSx lines can be changed by

setting the CSCFG bit in the SYSCON register. By

default the CSx lines change half a CPU clock

cycle after the rising edge of ALE (20ns @ fCPU =

25 MHz). With the CSCFG bit set (section

Figure VII -), the CSx lines change with the rising

edge of ALE. In this case, the CSx lines and

address lines change at the same time.

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