ST10F163 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST10F163 Datasheet PDF : 58 Pages
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ST10F163
X - PARALLEL PORTS
The ST10F163 provides up to 77 I/O lines which
are organized into six input/output ports and one
input port. All port lines are bit-addressable, and all
input/output lines are individually (bit-wise) pro-
grammable as, either inputs or outputs via direction
registers. The I/O ports are true bidirectional ports
which are switched to high impedance state when
configured as inputs. The output drivers of three I/
O ports can be configured (pin by pin) for push/pull
operation or open-drain operation via control regis-
ters. During the internal reset, all port pins are con-
figured as inputs. All port lines have associated,
programmable, alternate input or output functions.
PORT0 and PORT1 may be used as address and
data lines when accessing external memory. Port 4
outputs the additional segment address bits A23/
19/17...A16 in systems where segmentation is
enabled to access more than 64 KBytes of mem-
ory. Port 6 provides optional bus arbitration signals
(BREQ, HLDA, HOLD) and chip select signals. Port
3 includes alternate functions of timers, serial inter-
faces, the optional bus control signal BHE and the
system clock output (CLKOUT). Port 5 is used for
timer control signals. All port lines that are not used
for these alternate functions may be used as gen-
eral purpose I/O lines.
XI - SERIAL CHANNELS
Serial communication with other microcontrollers,
processors, terminals or external peripheral com-
ponents is provided by two serial interfaces, an
Asynchronous/Synchronous Serial Channel
(ASC0) and a Synchronous Serial Port (SSP).
ASC0: The table below shows the baud rates for
the asynchronous/synchronous serial channel.
A dedicated baud rate generator is used to set up
all standard baud rates without oscillator tuning. 3
separate interrupt vectors are provided for trans-
mission, reception, and erroneous reception. In
asynchronous mode, 8- or 9-bit data frames are
transmitted or received, preceded by a start bit
and terminated by one or two stop bits. For multi-
processor communication, a mechanism to distin-
guish address from data bytes has been included
(8-bit data + wake up bit mode). In synchronous
mode, the ASC0 transmits or receives bytes (8
bits) synchronously to a shift clock which is gener-
ated by the ASC0. The ASC0 always shifts the
LSB first. A loop back option is available for testing
purposes. A number of optional hardware error
detection capabilities have been included to
increase the reliability of data transfers. A parity
bit can automatically be generated on transmis-
sion or be checked on reception. Framing error
detection allows to recognize data frames with
missing stop bits. An overrun error will be gener-
ated, if the last character received has not been
read out of the receive buffer register by the time
the reception of a new character is complete.
Table 10 : Commonly used baud rates by reload value and deviation errors
S0BRS = ‘0’, fCPU = 25MHz
S0BRS = ‘1’, fCPU = 25MHz
Baud Rate
(Baud)
Deviation Error
Reload Value
Baud Rate
(Baud)
Deviation Error
Reload Value
781250
56000
38400
19200
9600
4800
2400
1200
600
95
±0.0%
+7.3%
+1.7%
+1.7%
+0.5%
+0.5%
+0.2%
+0.0%
+0.0%
+0.4%
/-0.4%
/ -3.1%
/ -0.8%
/ -0.8%
/ -0.1%
/ -0.1%
/ -0.1%
/ -0.1%
/ 0.4%
0000H
000CH / 000DH
0013H / 0014H
0027H / 0028H
0050H/ 0051H
00A1H / 00A2H
0144H / 0145H
028AH / 028BH
0515H / 0516H
1FFFH / 1FFFH
520833
56000
38400
19200
9600
4800
2400
1200
600
75
63
±0.0%
+3.3%
+4.3%
+0.5%
+0.5%
+0.5%
+0.0%
+0.0%
+0.0%
+0.0%
+0.9%
/ -7.0%
/ -3.1%
/ -3.1%
/ -1.4%
/ -0.5%
/ -0.5%
/ -0.2%
/ -0.1%
/ 0.0%
/ 0.9%
0000H
0008H / 0009H
000CH / 000DH
001AH / 001BH
0035H / 0036H
006BH / 006CH
00D8H / 00D9H
01B1H / 01B2H
0363H / 0364H
1B1FH / 1B20H
1FFFH / 1FFFH
Note The deviation errors given in the table above are rounded. Using a baudrate crystal will provide correct baudrates without deviation errors.
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