ST10F163
SSP: The Synchronous Serial Port provides
high-speed serial communication with external
slave devices such as EEPROM. The SSP trans-
mits 1...3 bytes or receives 1 byte after sending
1...3 bytes synchronously to a shift clock which is
generated by the SSP.
The SSP can start shifting with the LSB or with the
MSB and is used to select shifting and latching
clock edges as well as the clock polarity. Up to two
chip select lines may be activated in order to direct
data transfers to one or both of two peripheral
devices.
Table 11 : Synchronous baud rate and SSPCKS reload values
SSPCKS Value
000
001
010
011
100
101
110
111
SSP clock = CPU clock divided by 2
SSP clock = CPU clock divided by 4
SSP clock = CPU clock divided by 8
SSP clock = CPU clock divided by 16
SSP clock = CPU clock divided by 32
SSP clock = CPU clock divided by 64
SSP clock = CPU clock divided by 128
SSP clock = CPU clock divided by 256
Synchronous baud rate
12.5 MBit/s
6.25 MBit/s
3.13 MBit/s
1.56 MBit/s
781 KBit/s
391 KBit/s
195 KBit/s
97.7 KBit/s
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