ST10F163
Table 14 : Special Function Register List (continued)
Name
Physical
Address
8-Bit
Address
Description
Reset
Value
S0TBIC
b F19Ch
S0TBUF
FEB0h
S0TIC
b FF6Ch
SP
FE12h
SSPCON0
EF00h
SSPCON1
EF02h
SSPRTB
EF04h
SSPTB H
EF06h
STKO V
FE14h
STKUN
FE16h
SYSCON
b FF12h
T2
T2CON
T2IC
T3
T3CON
T3IC
T4
T4CON
T4IC
T5
T5CON
T5IC
T6
T6CON
T6IC
TFR
WDT
WDTCO N
FE40h
b FF40h
b FF60h
FE42h
b FF42h
b FF62h
FE44h
b FF44h
b FF64h
FE46h
b FF46h
b FF66h
FE48h
b FF48h
b FF68h
b FFACh
FEAEh
FFAEh
XP1IC
XP3IC
ZEROS
b F18Eh
b F19Eh
b FF1Ch
E
CEh Serial Channel 0 Transmit Buffer Interrupt Control 0000h
Reg
58h Serial Channel 0 Transmit Buffer Register (write 00h
only)
B6h Serial Channel 0 Transmit Interrupt Control Register 0000h
09h CPU System Stack Pointer Register
FC00h
X
--- SSP Control Register 0
0000h
X
--- SSP Control Register 1
0000h
X
--- SSP Receive/Transmit Buffer
XXXXh
X
--- SSP Transmit Buffer High
XXXXh
0Ah CPU Stack Overflow Pointer Register
FA00h
0Bh CPU Stack Underflow Pointer Register
FC00h
89h CPU System Configuration Register
0xx0h2)
20h GPT1 Timer 2 Register
0000h
A0h GPT1 Timer 2 Control Register
0000h
B0h GPT1 Timer 2 Interrupt Control Register
0000h
21h GPT1 Timer 3 Register
0000h
A1h GPT1 Timer 3 Control Register
0000h
B1h GPT1 Timer 3 Interrupt Control Register
0000h
22h GPT1 Timer 4 Register
0000h
A2h GPT1 Timer 4 Control Register
0000h
B2h GPT1 Timer 4 Interrupt Control Register
0000h
23h GPT2 Timer 5 Register
0000h
A3h GPT2 Timer 5 Control Register
0000h
B3h GPT2 Timer 5 Interrupt Control Register
0000h
24h GPT2 Timer 6 Register
0000h
A4h GPT2 Timer 6 Control Register
0000h
B4h GPT2 Timer 6 Interrupt Control Register
0000h
D6h Trap Flag Register
0000h
57h Watchdog Timer Register (read only)
0000h
D7h Watchdog Timer Control Register
000xh3)
E
C7h SSP Interrupt Control Register
0000h
E
CFh PLL unlock Interrupt Control Register
0000h
8Eh Constant Value 0’s Register (read only)
0000h
1. The value depends on the silicon revision and is given in the errata sheet.
2. The system configuration is selected during reset.
3. Bit WDTR indicates a watchdog timer triggered reset.
30/58