ST10F163 View Datasheet(PDF) - STMicroelectronics
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ST10F163 Datasheet PDF : 58 Pages
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Figure 22 : CLKOUT and READY
CLKOUT
ALE
Running cycle 1)
t32
t33
t30
t34
t31
ST10F163
READY
waitstate
MUX/Tristate 6)
t29
7)
Command
RD, WR
Sync
READY
Async
READY
2)
t35 t36
t58 t59
3)
3)
t58 t59
3)
t37
5)
t35 t36
3)
t604)
see 6)
1. Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).
2. The leading edge of the respective command depends on RW-delay.
3. READY sampled HIGH at this sampling point generates a READY controlled waitstate, READY sampled LOW at this sampling point ter-
minates the currently running bus cycle.
4. READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR).
5. If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (e.g. because CLKOUT is
not enabled), it must fulfill t 37 in order to be safely synchronized. This is guaranteed, if READY is removed in response to the command
(see Note 4)).
6. Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may be inserted here.
For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC waitstate this delay is
zero.
7. The next external bus cycle may start here.
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