ST10F163 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST10F163 Datasheet PDF : 58 Pages
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ST10F163
XVI.4.13 - External bus arbitration
VDD = 5 V ± 10%
VSS = 0 V
TA = 0 to +70 °C
CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF
CL (for Port 6, CS) = 100 pF
Parameter
Symbol
HOLD input setup time to CLKOUT
CLKOUT to HLDA high or BREQ low delay
CLKOUT to HLDA low or BREQ high delay
CSx release
CSx drive
Other signals release
Other signals drive
t61 SR
t62 CC
t63 CC
t64 CC
t65 CC
t66 CC
t67 CC
Figure 23 : External bus arbitration, releasing the bus
Max. CPU Clock
= 25MHz
min.
20
–
–
–
-4
–
-4
max.
–
20
20
20
24
20
24
Variable CPU Clock
1/2TCL = 1 to 25MHz
min.
20
–
–
–
-4
–
-4
max.
–
ns
20
ns
20
ns
20
ns
24
ns
20
ns
24
ns
CLKOUT
t61
HOLD
HLDA
1)
BREQ
CSx
(On P6.x)
Other
Signals
t63
t62
2)
t64
3)
t66
1)
1. The ST10F163 will complete the currently running bus cycle before granting bus access.
2. This is the first possibility for BREQ to get active.
3. The CS outputs will be resistive high (pullup) after t64.
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