Figure 26 : SSP read timing
1)
SSPCLK
SSPCEx
SSPDAT
t210
t209
last Wr. Bit
ST10F163
2)
t211
1st.In Bit
t206
3)
t212
Lst.In Bit
The transition of shift and latch edge of SSPCLK is programmable. This figure uses the falling edge as shift edge (drawn bold).
The bit timing is repeated for all bits to be transmitted or received.
The active level of the chip enable lines is programmable. This figure uses an active low CE (drawn bold).
At the end of a transmission or reception the CE signal is disabled in single transfer mode. In continuous transfer mode it remains active.
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