T28F016SA-080 View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
T28F016SA-080 Datasheet PDF : 55 Pages
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E
28F016SA
NOTES:
CE# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high.
1. Read timings during data program and block erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, but not 100% tested.
4. Data program/block erase durations are measured to valid Status Register data.
5. Word/byte program operations are typically performed with 1 programming pulse.
6. Address and data are latched on the rising edge of WE# for all command write operations.
7. This information will be available in a technical paper. Please call Intel’s Application Hotline or your local Intel sales office
for more information.
DEEP
POWER-DOWN
V IH
ADDRESSES (A)
NOTE 1 V IL
WRITE DATA-WRITE OR
ERASE SETUP COMMAND
t AVAV
WRITE VALID ADDRESS
& DATA (DATA-WRITE) OR
ERASE CONFIRM COMMAND
AUTOMATED DATA-WRITE
OR ERASE DELAY
WRITE READ EXTENDED
REGISTER COMMAND
A IN
t AVWH
t WHAX
V IH
ADDRESSES (A)
NOTE 2 V IL
t AVAV
A IN
t AVWH
t WHAX
NOTE 3
V IH
CEx # (E)
NOTE 4 V IL
V IH
OE# (G) V IL
t ELWL
t WHEH
t WHGL
READ EXTENDED
STATUS REGISTER DATA
A=RA
READ COMPATIBLE
STATUS REGISTER DATA
t WHWL
V IH
WE# (W)
V IL
t WLWH
t DVWH
t WHDX
V IH
HIGH Z
DATA (D/Q)
V IL
t PHWL
D IN
D IN
t WHQV1,2
D IN
t GHWL
D OUT
D IN
V OH
RY/BY# (R)
V OL
t WHRL
V IH
RP# (P)
V IL
t RHPL
NOTE 5
V PPH
V PP(V)
V PPL
V IN
V IL
t VPWH
t QVVL
NOTES:
1. This address string depicts data program/block erase cycles with corresponding verification via ESRD.
2. This address string depicts data program/block erase cycles with corresponding verification via CSRD.
3. This cycle is invalid when using CSRD for verification during data program/block erase operations.
4. CEX# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high.
5. RP# low transition is only to show tRHPL; not valid for above read and program cycles.
0489_14
Figure 15. AC Waveforms for Command Write Operations
41
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