AD5763CSUZ(RevC) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD5763CSUZ
(Rev.:RevC)

Complete Dual, 16-Bit High Accuracy, Serial Input, ±5 V DAC

Analog Devices 

AD5763

TRANSFER FUNCTION

Table 7 shows the ideal input code to output voltage relationship

for the AD5763 for both offset binary and twos complement

data coding.

Table 7. Ideal Output Voltage to Input Code Relationship

Digital Input

Analog Output

Offset Binary Data Coding

MSB

LSB VOUTx

1111

1000

1000

1111

0000

0000

1111

0000

0000

1111

0001

0000

+2VREF × (32,767/32,768)

+2VREF × (1/32,768)

0V

0111 1111 1111

0000 0000 0000

1111

0000

−2VREF × (1/32,768)

−2VREF × (32,767/32,768)

Twos Complement Data Coding

MSB

LSB VOUTx

0111

0000

0000

1111

0000

0000

1111

0000

0000

1111

0001

0000

+2VREF × (32,767/32,768)

+2VREF × (1/32,768)

0V

1111 1111 1111

1000 0000 0000

1111

0000

−2VREF × (1/32,768)

−2VREF × (32,767/32,768)

Data Sheet

The output voltage expression for the AD5763 is given by

VOUTx

=

−2 × VREFIN

+

4 × VREFIN

⎡D⎤

⎢⎣65,536 ⎥⎦

where:

D is the decimal equivalent of the code loaded to the DAC.

VREFIN is the reference voltage applied at the REFA and REFB pins.

ASYNCHRONOUS CLEAR (CLR)

CLR is a negative edge triggered clear that allows the outputs to

be cleared to either 0 V (twos complement coding) or negative

full scale (offset binary coding). It is necessary to keep CLR low

for a minimum amount of time for the operation to complete (see

Figure 2). When the CLR signal is returned high, the output

remains at the cleared value until a new value is programmed.

If at power-on, CLR is at 0 V, all DAC outputs are updated with

the clear value. A clear can also be initiated through software by

writing a command, 0x04XXXX, to the AD5763.

Table 8. Input Register Format

MSB

DB23 DB22 DB21 DB20

R/W 0

REG2 REG1

DB19

REG0

DB18

A2

DB17

A1

DB16

A0

LSB

DB15:DB0

Data

Table 9. Input Register Bit Functions

Bit

Description

R/W

Indicates a read from or a write to the addressed register

REG2, REG1, REG0

These bits are used in association with the address bits to determine if a read or write operation is sent to the

function register, data register, offset register, or gain register

REG2 REG1 REG0

Function

0

0

0

Function register

0

1

0

Data register

0

1

1

Coarse gain register

1

0

0

Fine gain register

1

0

1

Offset register

A2, A1, A0

These bits are used to decode the DAC channels

A2

A1

A0

Channel Address

0

0

0

DAC A

0

0

1

DAC B

1

0

0

Both DACs

D15:D0

Data bits

Rev. C | Page 18 of 28

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