AD5763CSUZ(RevC) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD5763CSUZ Datasheet PDF : 28 Pages
| |||
Data Sheet
AD5763
FUNCTION REGISTER
The function register is addressed by setting the three REG bits to 000. The values written to the address bits and the data bits determine
the function addressed. The functions available via the function register are outlined in Table 10 and Table 11.
Table 10. Function Register Options
REG2 REG1 REG0 A2 A1 A0
0
0
0
000
0
0
0
001
DB15:DB6
Don’t care
0
0
0
100
0
0
0
101
DB5
Local-ground-offset
adjust
DB4
DB3
NOP, data = don’t care
D1
direction
D1
value
Clear, data = don’t care
Load, data = don’t care
DB2
D0
direction
DB1
D0
value
DB0
SDO
disable
Table 11. Explanation of Function Register Options
Option
Description
NOP
No operation instruction used in readback operations.
Local-Ground-
Offset Adjust
Set by the user to enable local-ground-offset adjust function. Cleared by the user to disable local-ground-offset adjust
function (default). See the
Design Features section for further details.
D0/D1 Direction Set by the user to enable D0, D1 as outputs. Cleared by the user to enable D0, D1 as inputs (default). See the
D0/D1 Value
SDO Disable
Clear
Load
Design Features section for further details.
I/O port status bits. Logic values written to these locations determine the logic outputs on the D0 and D1 pins when
configured as outputs. These bits indicate the status of the D0 and D1 pins when the I/O port is active as an input.
When enabled as inputs, these bits are don’t cares during a write operation.
Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default).
Addressing this function resets the DAC outputs to 0 V in twos complement mode and negative full scale in binary mode.
Addressing this function updates the DAC registers and, consequently, the analog outputs.
DATA REGISTER
The data register is addressed by setting the three REG bits to 010. The DAC address bits select with which DAC channel the data transfer
is to take place (see Table 9). The data bits are in Position DB15 to Position DB0 as shown in Table 12.
Table 12. Programming the Data Register
REG2
REG1
REG0
0
1
0
A2
A1
A0
DAC address
DB15 … DB0
16-bit DAC data
COARSE GAIN REGISTER
The coarse gain register is addressed by setting the three REG bits to 011. The DAC address bits select with which DAC channel the data
transfer is to take place (see Table 9). The coarse gain register is a 2-bit register and allows the user to select the output range of each DAC
as shown in Table 13 and Table 14.
Table 13. Programming the Coarse Gain Register
REG2
REG1
REG0
A2
0
1
1
A1
A0
DAC address
DB15:DB2
Don’t care
DB1
DB0
CG1
CG0
Table 14. Output Range Selection
Output Range
±4.096 V (Default)
±4.20103 V
±4.31158 V
CG1
CG0
0
0
0
1
1
0
Rev. C | Page 19 of 28
Share Link: 