ADE3700XT View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ADE3700XT Datasheet PDF : 89 Pages
| |||
Global Control
Register Name
GLBL_CLK_INV
GLBL_CLK_ENABLE_0
GLBL_ANA_PWR
GLBL_XK_SRST
GLBL_I2C_CTRL
GLBL_XTAL_CTRL
GLBL_SCLK_SYNTH_CTRL
ADE3700
Table 4: Global Registers (Sheet 2 of 4)
Addr.
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
mode Bits
[7:5]
R/W
[4]
R/W
[3]
R/W
[2]
R/W
[1]
R/W
[0]
[7:1]
R/W
[0]
[7:5]
R/W
[4]
R/W
[3]
R/W
[2]
[1:0]
[7:3]
R/W
[2]
R/W
[1]
R/W
[0]
[7:3]
R/W
[2]
R/W
[1]
R/W
[0]
[7:1]
R/W
[0]
[7:5]
R/W
[4:3]
R/W
[2]
R/W
[1]
R/W
[0]
Default
Description
0x0
Reserved
0x0
Invert LLPLL control clock
0x0
Invert LLPLL zero clock
0x0
Invert ADC sample clock
0x0
Invert DOT clock
0x0
Invert input clock
0x0
Reserved
0x1
Clock enable async override
0x0
Reserved
0x1
Blue ADC power down
0x1
Green ADC power down
0x1
Red ADC power down
0x0
Reserved
0x0
Reserved
0x0
SMEAS block reset, synchronous to XCLK
0x0
SRT block reset, synchronous to XCLK
0x0
Frame Sync block reset, synchronous to
XCLK
0x0
Reserved
0x0
Disable I2C auto increment
0x0
SDA PMOS enable
0x0
bypass I2C filter
0x0
Reserved
0x1
crystal oscillator enable
0x0
Reserved
0x0
XTAL frequency multiplier NDIV
0x0: fXCLK = 54MHz
0x1: fXCLK = 27MHz (normal)
0x2: fXCLK = 13.5MHz
0x3: Reserved
0x0
SCLK frequency synthesizer EXT_PLL
(normal operation = 0)
0x0
SCLK frequency synthesizer PLL_SEL
(normal operation = 1)
0x1
SCLK freq synth control disable (normal
operation = 0)
14/89
Share Link: 