ADE3700XT View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ADE3700XT Datasheet PDF : 89 Pages
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ADE3700
Register Name
GLBL_SCLK_MD_SD
GLBL_SCLK_PE_L
GLBL_SCLK_PE_H
GLBL_TST_CTRL
GLBL_COMP_PAD_CTRL
GLBL_SCLK_CTRL
GLBL_BPAD_EN
GLBL_IK_SRST
GLBL_SHADOW_EN
Global Control
Table 4: Global Registers (Sheet 3 of 4)
Addr.
0x000A
0x000B
0x000C
0x000D
0x000E
0x0010
0x0011
0x0020
0x0021
mode Bits
R/W
[7:3]
R/W
[2:0]
R/W
[7:0]
R/W
[7:0]
[7:1]
R/W
[0]
[7:2]
R/W
[1]
R/W
[0]
[7:5]
R/W
[4]
[3]
R/W
[2:0]
R/W
[3:0]
R/W
[4]
R/W
[7]
R/W
[6]
R/W
[5]
R/W
[4]
R/W
[3]
R/W
[2]
R/W
[1]
R/W
[0]
[7:1]
R/W
[0]
Default
Description
0x0
SCLK frequency synthesizer MD, range is
[16,31]
0x0
SCLK frequency synthesizer SDIV, range is
[0,7]
0x0
SCLK frequency synthesizer PE, range is
[0, 32767]
0x0
Reserved
0x0
functional test mode enable
0x0
Reserved
0x0
Compensation pad TQ (test mode)
0x1
Compensation pad EN (enable)
0x0
Reserved
0x0
invert SCLK
0x0
Reserved
0x0
SCLK source select
0x0: TESTCLK pin
0x1: SCLK freq synth
0x2: FM freq synth (normal)
0x3: INCLK source
0x4: CLKIN pin
0x5: crystal clock
0x6: 0
0x7: Reserved
0x0
For each bit n (0 to 3) in the LS nibble,
0: TCON[n] pin is TCON output
1: TCON[n] pin is input for testing
0x0
Port B input mode enable (production test
only)
0x0
Reserved
0x0
DFT block reset synchronous to INCLK
0x0
ADC block reset synchronous to INCLK
0x0
SCALER block reset synchronous to
INCLK
0x0
Reserved
0x0
Reserved
0x0
DMEAS block reset synchronous to INCLK
0x0
SMUX block reset synchronous to INCLK
0x0
Reserved
0x0
Shadow registers sync on frame boundary
15/89
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