ADE3700XT View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ADE3700XT Datasheet PDF : 89 Pages
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ADE3700
Line Lock PLL
Table 7: Line Lock PLL Registers (Sheet 1 of 4)
Register Name
LLK_PLL_CLEAR
Addr
0x0800
LLK_PLL_CTRL
0x0801
LLK_PLL_MFACTOR_L
LLK_PLL_MFACTOR_H
LLK_PLL_HPERIOD_L
LLK_PLL_HPERIOD_H
LLK_PLL_PHASE_RATE_INIT_0
LLK_PLL_PHASE_RATE_INIT_1
0x0802
0x0803
0x0804
0x0805
0x0806
0x0807
LLK_PLL_PHASE_RATE_INIT_2
0x0808
LLK_PLL_PHASE_RATE_INIT_3
0x0809
LLK_PLL_PHASE_RATE_INIT_WR 0x080A
Mode Bits
[7:6]
R/W
[5]
R/W
[4]
R/W
[3]
R/W
[2]
R/W
[1]
R/W
[0]
R/W
[7]
R/W
[6]
R/W
[5]
R/W
[4]
R/W
[3]
R/W
[2]
R/W
[1]
R/W
[0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:1]
[0]
Default
Description
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0280
Reserved
master reset
reset the PLL synthetic sync
reset PLL offset
reset PLL accumulator
reset the low pass filter
reset the PLL phase error
Reserved
zero clock delay enable
0: normal
1: diagnostic mode -- PLL uses only fine
error
0: normal
1: diagnostic -- coarse error is multiplied by
2
input hsync edge selection
0: rising edge
1: falling edge
sync on green input selection
0: composite sync (HSYNC pin)
1: sync on green (CSYNC pin)
0: normal
1: divide PLL clock by 2
0: normal
1: free-running mode
number of clocks in a line
0x0040 pulse width of synthetic hsync
0x0
initial phase rate
fout = fxtal * 227+NDIV / phase_rate
Reserved
When written to 1, the pll phase rate is
initialized with the initial phase rate
register. Self clearing.
19/89
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