ADE3000SX View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ADE3000SX Datasheet PDF : 88 Pages
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ADE3XXX
Output Mux Block
Register Name
APC_APC0
APC_APC1
Table 28: APC Registers
Addr
0x0C20
0x0C21
Mode Bits
[7]
R/W
[6:5]
R/W
[4:1]
R/W
[0]
[7:2]
R/W
[1]
R/W
[0]
Default
Description
Reserved
0x0
Frame Modulation Period - 1
0x0
0x0 - 0x3: 8b Out
0x4: 4-bit Output
0x5: 5-bit Output
0x6: 6-bit Output
0x7: 7-bit Output
0x8: 8-bit Output
0x0
0: normal
1: disable APC -- truncate LSBs
Reserved
0x0
Offset the Phase LUT
0x0
Offset the Dither LUT
2.23 Output Mux Block
Table 29: Output Mux Registers (Sheet 1 of 3)
Register Name
OMUX_CTRL_0
OMUX_CTRL_1
Addr
0x0C30
0x0C31
Mode Bits
R/W
[7]
R/W
[6:4]
R/W
[3]
R/W
[2]
R/W
[1]
R/W
[0]
R/W
[7]
R/W
[6]
R/W
[5]
R/W
[4]
R/W
[3]
R/W
[2]
R/W
[1]
R/W
[0]
Default
Description
0x0
in 2 ppc,
0: data invert for A+B comb.
1: data invert A/B separate
0x0
0x0 - 0x4: right shift per 8b R/G/B
0x5 - 0x7: Reserved
0x0
0: normal
1: flip MSBs to LSBs
0x0
0: normal
1: swap R and B data
0x0
0: in 1 ppc, A channel active
0: in 2 ppc, Left on A, Right on B
1: in 1 ppc, B channel active
1: 2ppc, Left on B, Right on A
0x0
0: single wide, one pix/clk (ppc)
1: double wide, two pix/clk
0x0
Vsync Output Polarity
0x0
Hsync Output Polarity
0x0
Data Enable Output Polarity
0x0
Clock Output Invert
0x0
Data Invert Output Polarity
0x0
Data Invert Enable
0x0
0: TCON outputs set to zero
1: TCON outputs active
0x0
0: all data outputs set to zero
1: output enabled
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