ADE3000SX View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ADE3000SX Datasheet PDF : 88 Pages
| |||
Output Mux Block
Register Name
OMUX_CTRL_2
OMUX_DLY_BA0
OMUX_ DLY_BA2
OMUX_ DLY_BA4
OMUX_ DLY_BA6
OMUX_ DLY_GA0
OMUX_ DLY_GA2
OMUX_ DLY_GA4
OMUX_ DLY_GA6
OMUX_ DLY_RA0
OMUX_ DLY_RA2
OMUX_ DLY_RA4
OMUX_ DLY_RA6
OMUX_ DLY_BB0
OMUX_ DLY_BB2
OMUX_ DLY_BB4
OMUX_ DLY_BB6
OMUX_ DLY_GB0
OMUX_ DLY_GB2
ADE3XXX
Table 29: Output Mux Registers (Sheet 2 of 3)
Addr
0x0C32
0x0C50
0x0C4F
0x0C4E
0x0C4D
0x0C4C
0x0C4B
0x0C4A
0x0C49
0x0C48
0x0C47
0x0C46
0x0C45
0x0C44
0x0C43
0x0C42
0x0C41
0x0C40
0x0C3F
Mode Bits
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
Default
Description
0x0
Seperate TCON Driven Invert Enable
0x0
TCON Driven Invert Pin Enable
0x0
RSDS enable
0x0
Per Pin Delay Enable
0x0
Resync on Vsync Falling Edge
0x0
Resync on Vsync Rising Edge
0x0
Resync on Hsync Falling Edge
0x0
Resync on Hsync Rising Edge
0x0
Delay for OBA1
0x0
Delay for OBA0
0x0
Delay for OBA3
0x0
Delay for OBA2
0x0
Delay for OBA5
0x0
Delay for OBA4
0x0
Delay for OBA7
0x0
Delay for OBA6
0x0
Delay for OGA1
0x0
Delay for OGA0
0x0
Delay for OGA3
0x0
Delay for OGA2
0x0
Delay for OGA5
0x0
Delay for OGA4
0x0
Delay for OGA7
0x0
Delay for OGA6
0x0
Delay for ORA1
0x0
Delay for ORA0
0x0
Delay for ORA3
0x0
Delay for ORA2
0x0
Delay for ORA5
0x0
Delay for ORA4
0x0
Delay for ORA7
0x0
Delay for ORA6
0x0
Delay for OBB1
0x0
Delay for OBB0
0x0
Delay for OBB3
0x0
Delay for OBB2
0x0
Delay for OBB5
0x0
Delay for OBB4
0x0
Delay for OBB7
0x0
Delay for OBB6
0x0
Delay for OGB1
0x0
Delay for OGB0
0x0
Delay for OGB3
0x0
Delay for OGB2
76/88
Share Link: 