ADE3000SX View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ADE3000SX

LCD Display Engines with Integrated DVI, ADC and YUV Ports

STMicroelectronics 

ADE3XXX

2.25 DFT Block

Register Name

DFT_TEST_MODE

DFT_MUX_OUT_MODE

DFT_FLOP_OUT_MODE

DFT_CLK_0UT_MODE

DFT_CLK_1_MODE

DFT_CLK_2_MODE

DFT_OUT_DISAB_0

DFT_OUT_DISAB_1

DFT_OUT_DISAB_2

DFT_OUT_DISAB_3

DFT_OUT_DISAB_4

DFT_OUT_DISAB_5

DFT_OUT_DISAB_6

DFT_OUT_DISAB_7

DFT_STIM_CTRL

DFT_STIM_EN_0

DFT Block

Table 31: DFT Registers (Sheet 1 of 2)

Addr

0x0F00

0x0F01

0x0F02

0x0F03

0x0F04

0x0F05

0x0F06

0x0F07

0x0F08

0x0F09

0x0F0A

0x0F0B

0x0F0C

0x0F0D

0x0F0E

0x0F0F

Mode Bits

[7:4]

R/W

[3]

R/W

[2]

R/W

[1]

R/W

[0]

[7:6]

R/W

[5:0]

[7:6]

R/W

[5:0]

R/W

[7:6]

R/W

[5:0]

R/W

[7:6]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

[5:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7:3]

[2]

[1]

[0]

[7:5]

[4]

[3]

[2:0]

[7:6]

[0]

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

Default

Description

Reserved

0x0

trigger video bus MFSR

0x0

enable output pin MFSR

0x0

clear output pin MFSR

0x0

output pin test override

Reserved

0x0

mux selector for output porta/b and syncs

Reserved

0x0

mux selector for synchronous digital debug

bus

0x0

divide-by selector for clocks to OCLK pin

fout = selected clock / (2 ^ value)

0x0

mux selector for clocks to OCLK pin

0x0

divide-by selector for clocks to CLKOUT pin

fout = selected clock / (2 ^ value)

0x0

mux selector for clocks to CLKOUTpin

0x0

disable porta red output in test mode

0x0

disable porta green output in test mode

0x0

disable porta blue output in test mode

0x0

disable portb red output in test mode

0x0

disable portb green output in test mode

0x0

disable portb blue output in test mode

0x0

disable tcon bits [4:0] in test mode

0x0

disable vert sync output in test mode

0x0

disable data enab output in test mode

0x0

disable horz sync output in test mode

Reserved

0x0

disable CLKOUT output in test mode

0x0

disable OCLK output in test mode

0x0

disable tcon bits [7:5] in test mode

Reserved

0x0

internal stimulus bus enable

0x0

SCL test stimulus enable

HDCP test stimulus enable

DVI test mode enable

DVI blue test stimulus enable

DVI green test stimulus enable

0x0

DVI red test stimulus enable

0x0

ADC test stimulus enable

0x0

YUV test stimulus enable

79/88

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